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  1. /*
  2.  * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup arm32mm
  30.  * @{
  31.  */
  32. /** @file
  33.  *  @brief Page fault related functions.
  34.  */
  35. #include <panic.h>
  36. #include <arch/exception.h>
  37. #include <arch/mm/page_fault.h>
  38. #include <mm/as.h>
  39. #include <genarch/mm/page_pt.h>
  40. #include <arch.h>
  41. #include <interrupt.h>
  42. #include <print.h>
  43.  
  44. /** Returns value stored in fault status register.
  45.  *
  46.  *  @return Value stored in CP15 fault status register (FSR).
  47.  */
  48. static inline fault_status_t read_fault_status_register(void)
  49. {
  50.     fault_status_union_t fsu;
  51.    
  52.     /* fault status is stored in CP15 register 5 */
  53.     asm volatile (
  54.         "mrc p15, 0, %[dummy], c5, c0, 0"
  55.         : [dummy] "=r" (fsu.dummy)
  56.     );
  57.    
  58.     return fsu.fs;
  59. }
  60.  
  61. /** Returns FAR (fault address register) content.
  62.  *
  63.  * @return FAR (fault address register) content (address that caused a page
  64.  *         fault)
  65.  */
  66. static inline uintptr_t read_fault_address_register(void)
  67. {
  68.     uintptr_t ret;
  69.    
  70.     /* fault adress is stored in CP15 register 6 */
  71.     asm volatile (
  72.         "mrc p15, 0, %[ret], c6, c0, 0"
  73.         : [ret] "=r" (ret)
  74.     );
  75.    
  76.     return ret;
  77. }
  78.  
  79. /** Decides whether the instruction is load/store or not.
  80.  *
  81.  * @param instr Instruction
  82.  *
  83.  * @return true when instruction is load/store, false otherwise
  84.  *
  85.  */
  86. static inline bool is_load_store_instruction(instruction_t instr)
  87. {
  88.     /* load store immediate offset */
  89.     if (instr.type == 0x2)
  90.         return true;
  91.    
  92.     /* load store register offset */
  93.     if ((instr.type == 0x3) && (instr.bit4 == 0))
  94.         return true;
  95.    
  96.     /* load store multiple */
  97.     if (instr.type == 0x4)
  98.         return true;
  99.    
  100.     /* oprocessor load/store */
  101.     if (instr.type == 0x6)
  102.         return true;
  103.    
  104.     return false;
  105. }
  106.  
  107. /** Decides whether the instruction is swap or not.
  108.  *
  109.  * @param instr Instruction
  110.  *
  111.  * @return true when instruction is swap, false otherwise
  112.  */
  113. static inline bool is_swap_instruction(instruction_t instr)
  114. {
  115.     /* swap, swapb instruction */
  116.     if ((instr.type == 0x0) &&
  117.         ((instr.opcode == 0x8) || (instr.opcode == 0xa)) &&
  118.         (instr.access == 0x0) && (instr.bits567 == 0x4) && (instr.bit4 == 1))
  119.         return true;
  120.    
  121.     return false;
  122. }
  123.  
  124. /** Decides whether read or write into memory is requested.
  125.  *
  126.  * @param instr_addr   Address of instruction which tries to access memory.
  127.  * @param badvaddr     Virtual address the instruction tries to access.
  128.  *
  129.  * @return Type of access into memory, PF_ACCESS_EXEC if no memory access is
  130.  *     requested.
  131.  */
  132. static pf_access_t get_memory_access_type(uint32_t instr_addr,
  133.     uintptr_t badvaddr)
  134. {
  135.     instruction_union_t instr_union;
  136.     instr_union.pc = instr_addr;
  137.  
  138.     instruction_t instr = *(instr_union.instr);
  139.  
  140.     /* undefined instructions */
  141.     if (instr.condition == 0xf) {
  142.         panic("page_fault - instruction does not access memory "
  143.             "(instr_code: %x, badvaddr:%x).", instr, badvaddr);
  144.         return PF_ACCESS_EXEC;
  145.     }
  146.  
  147.     /* load store instructions */
  148.     if (is_load_store_instruction(instr)) {
  149.         if (instr.access == 1) {
  150.             return PF_ACCESS_READ;
  151.         } else {
  152.             return PF_ACCESS_WRITE;
  153.         }
  154.     }
  155.  
  156.     /* swap, swpb instruction */
  157.     if (is_swap_instruction(instr)) {
  158.         return PF_ACCESS_WRITE;
  159.     }
  160.  
  161.     panic("page_fault - instruction doesn't access memory "
  162.         "(instr_code: %x, badvaddr:%x).", instr, badvaddr);
  163.  
  164.     return PF_ACCESS_EXEC;
  165. }
  166.  
  167. /** Handles "data abort" exception (load or store at invalid address).
  168.  *
  169.  * @param exc_no    Exception number.
  170.  * @param istate    CPU state when exception occured.
  171.  */
  172. void data_abort(int exc_no, istate_t *istate)
  173. {
  174.     fault_status_t fsr __attribute__ ((unused)) =
  175.         read_fault_status_register();
  176.     uintptr_t badvaddr = read_fault_address_register();
  177.  
  178.     pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
  179.  
  180.     int ret = as_page_fault(badvaddr, access, istate);
  181.  
  182.     if (ret == AS_PF_FAULT) {
  183.         print_istate(istate);
  184.         printf("page fault - pc: %x, va: %x, status: %x(%x), "
  185.             "access:%d\n", istate->pc, badvaddr, fsr.status, fsr,
  186.             access);
  187.        
  188.         fault_if_from_uspace(istate, "Page fault: %#x.", badvaddr);
  189.         panic("Page fault.");
  190.     }
  191. }
  192.  
  193. /** Handles "prefetch abort" exception (instruction couldn't be executed).
  194.  *
  195.  * @param exc_no    Exception number.
  196.  * @param istate    CPU state when exception occured.
  197.  */
  198. void prefetch_abort(int exc_no, istate_t *istate)
  199. {
  200.     int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);
  201.  
  202.     if (ret == AS_PF_FAULT) {
  203.         printf("prefetch_abort\n");
  204.         print_istate(istate);
  205.         panic("page fault - prefetch_abort at address: %x.",
  206.             istate->pc);
  207.     }
  208. }
  209.  
  210. /** @}
  211.  */
  212.