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  1. /*
  2.  * Copyright (c) 2001-2004 Jakub Jermar
  3.  * Copyright (c) 2005 Sergey Bondari
  4.  * All rights reserved.
  5.  *
  6.  * Redistribution and use in source and binary forms, with or without
  7.  * modification, are permitted provided that the following conditions
  8.  * are met:
  9.  *
  10.  * - Redistributions of source code must retain the above copyright
  11.  *   notice, this list of conditions and the following disclaimer.
  12.  * - Redistributions in binary form must reproduce the above copyright
  13.  *   notice, this list of conditions and the following disclaimer in the
  14.  *   documentation and/or other materials provided with the distribution.
  15.  * - The name of the author may not be used to endorse or promote products
  16.  *   derived from this software without specific prior written permission.
  17.  *
  18.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28.  */
  29.  
  30. /** @addtogroup ia32
  31.  * @{
  32.  */
  33. /** @file
  34.  */
  35.  
  36. #ifndef KERN_ia32_ASM_H_
  37. #define KERN_ia32_ASM_H_
  38.  
  39. #include <arch/pm.h>
  40. #include <arch/types.h>
  41. #include <typedefs.h>
  42. #include <config.h>
  43.  
  44. extern uint32_t interrupt_handler_size;
  45.  
  46. extern void paging_on(void);
  47.  
  48. extern void interrupt_handlers(void);
  49.  
  50. extern void enable_l_apic_in_msr(void);
  51.  
  52.  
  53. extern void asm_delay_loop(uint32_t t);
  54. extern void asm_fake_loop(uint32_t t);
  55.  
  56.  
  57. /** Halt CPU
  58.  *
  59.  * Halt the current CPU.
  60.  *
  61.  */
  62. static inline void cpu_halt(void)
  63. {
  64.     asm volatile (
  65.         "0:\n"
  66.         "   hlt\n"
  67.         "   jmp 0b\n"
  68.     );
  69. }
  70.  
  71. static inline void cpu_sleep(void)
  72. {
  73.     asm volatile ("hlt\n");
  74. }
  75.  
  76. #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
  77.     { \
  78.         unative_t res; \
  79.         asm volatile ( \
  80.             "movl %%" #reg ", %[res]" \
  81.             : [res] "=r" (res) \
  82.         ); \
  83.         return res; \
  84.     }
  85.  
  86. #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
  87.     { \
  88.         asm volatile ( \
  89.             "movl %[regn], %%" #reg \
  90.             :: [regn] "r" (regn) \
  91.         ); \
  92.     }
  93.  
  94. GEN_READ_REG(cr0)
  95. GEN_READ_REG(cr2)
  96. GEN_READ_REG(cr3)
  97. GEN_WRITE_REG(cr3)
  98.  
  99. GEN_READ_REG(dr0)
  100. GEN_READ_REG(dr1)
  101. GEN_READ_REG(dr2)
  102. GEN_READ_REG(dr3)
  103. GEN_READ_REG(dr6)
  104. GEN_READ_REG(dr7)
  105.  
  106. GEN_WRITE_REG(dr0)
  107. GEN_WRITE_REG(dr1)
  108. GEN_WRITE_REG(dr2)
  109. GEN_WRITE_REG(dr3)
  110. GEN_WRITE_REG(dr6)
  111. GEN_WRITE_REG(dr7)
  112.  
  113. /** Byte to port
  114.  *
  115.  * Output byte to port
  116.  *
  117.  * @param port Port to write to
  118.  * @param val Value to write
  119.  *
  120.  */
  121. static inline void pio_write_8(ioport8_t *port, uint8_t val)
  122. {
  123.     asm volatile (
  124.         "outb %b[val], %w[port]\n"
  125.         :: [val] "a" (val), [port] "d" (port)
  126.     );
  127. }
  128.  
  129. /** Word to port
  130.  *
  131.  * Output word to port
  132.  *
  133.  * @param port Port to write to
  134.  * @param val Value to write
  135.  *
  136.  */
  137. static inline void pio_write_16(ioport16_t *port, uint16_t val)
  138. {
  139.     asm volatile (
  140.         "outw %w[val], %w[port]\n"
  141.         :: [val] "a" (val), [port] "d" (port)
  142.     );
  143. }
  144.  
  145. /** Double word to port
  146.  *
  147.  * Output double word to port
  148.  *
  149.  * @param port Port to write to
  150.  * @param val Value to write
  151.  *
  152.  */
  153. static inline void pio_write_32(ioport32_t *port, uint32_t val)
  154. {
  155.     asm volatile (
  156.         "outl %[val], %w[port]\n"
  157.         :: [val] "a" (val), [port] "d" (port)
  158.     );
  159. }
  160.  
  161. /** Byte from port
  162.  *
  163.  * Get byte from port
  164.  *
  165.  * @param port Port to read from
  166.  * @return Value read
  167.  *
  168.  */
  169. static inline uint8_t pio_read_8(ioport8_t *port)
  170. {
  171.     uint8_t val;
  172.    
  173.     asm volatile (
  174.         "inb %w[port], %b[val]\n"
  175.         : [val] "=a" (val)
  176.         : [port] "d" (port)
  177.     );
  178.    
  179.     return val;
  180. }
  181.  
  182. /** Word from port
  183.  *
  184.  * Get word from port
  185.  *
  186.  * @param port Port to read from
  187.  * @return Value read
  188.  *
  189.  */
  190. static inline uint16_t pio_read_16(ioport16_t *port)
  191. {
  192.     uint16_t val;
  193.    
  194.     asm volatile (
  195.         "inw %w[port], %w[val]\n"
  196.         : [val] "=a" (val)
  197.         : [port] "d" (port)
  198.     );
  199.    
  200.     return val;
  201. }
  202.  
  203. /** Double word from port
  204.  *
  205.  * Get double word from port
  206.  *
  207.  * @param port Port to read from
  208.  * @return Value read
  209.  *
  210.  */
  211. static inline uint32_t pio_read_32(ioport32_t *port)
  212. {
  213.     uint32_t val;
  214.    
  215.     asm volatile (
  216.         "inl %w[port], %[val]\n"
  217.         : [val] "=a" (val)
  218.         : [port] "d" (port)
  219.     );
  220.    
  221.     return val;
  222. }
  223.  
  224. /** Enable interrupts.
  225.  *
  226.  * Enable interrupts and return previous
  227.  * value of EFLAGS.
  228.  *
  229.  * @return Old interrupt priority level.
  230.  *
  231.  */
  232. static inline ipl_t interrupts_enable(void)
  233. {
  234.     ipl_t v;
  235.    
  236.     asm volatile (
  237.         "pushf\n"
  238.         "popl %[v]\n"
  239.         "sti\n"
  240.         : [v] "=r" (v)
  241.     );
  242.    
  243.     return v;
  244. }
  245.  
  246. /** Disable interrupts.
  247.  *
  248.  * Disable interrupts and return previous
  249.  * value of EFLAGS.
  250.  *
  251.  * @return Old interrupt priority level.
  252.  *
  253.  */
  254. static inline ipl_t interrupts_disable(void)
  255. {
  256.     ipl_t v;
  257.    
  258.     asm volatile (
  259.         "pushf\n"
  260.         "popl %[v]\n"
  261.         "cli\n"
  262.         : [v] "=r" (v)
  263.     );
  264.    
  265.     return v;
  266. }
  267.  
  268. /** Restore interrupt priority level.
  269.  *
  270.  * Restore EFLAGS.
  271.  *
  272.  * @param ipl Saved interrupt priority level.
  273.  *
  274.  */
  275. static inline void interrupts_restore(ipl_t ipl)
  276. {
  277.     asm volatile (
  278.         "pushl %[ipl]\n"
  279.         "popf\n"
  280.         :: [ipl] "r" (ipl)
  281.     );
  282. }
  283.  
  284. /** Return interrupt priority level.
  285.  *
  286.  * @return EFLAFS.
  287.  *
  288.  */
  289. static inline ipl_t interrupts_read(void)
  290. {
  291.     ipl_t v;
  292.    
  293.     asm volatile (
  294.         "pushf\n"
  295.         "popl %[v]\n"
  296.         : [v] "=r" (v)
  297.     );
  298.    
  299.     return v;
  300. }
  301.  
  302. /** Write to MSR */
  303. static inline void write_msr(uint32_t msr, uint64_t value)
  304. {
  305.     asm volatile (
  306.         "wrmsr"
  307.         :: "c" (msr), "a" ((uint32_t) (value)),
  308.            "d" ((uint32_t) (value >> 32))
  309.     );
  310. }
  311.  
  312. static inline uint64_t read_msr(uint32_t msr)
  313. {
  314.     uint32_t ax, dx;
  315.    
  316.     asm volatile (
  317.         "rdmsr"
  318.         : "=a" (ax), "=d" (dx)
  319.         : "c" (msr)
  320.     );
  321.    
  322.     return ((uint64_t) dx << 32) | ax;
  323. }
  324.  
  325.  
  326. /** Return base address of current stack
  327.  *
  328.  * Return the base address of the current stack.
  329.  * The stack is assumed to be STACK_SIZE bytes long.
  330.  * The stack must start on page boundary.
  331.  *
  332.  */
  333. static inline uintptr_t get_stack_base(void)
  334. {
  335.     uintptr_t v;
  336.    
  337.     asm volatile (
  338.         "andl %%esp, %[v]\n"
  339.         : [v] "=r" (v)
  340.         : "0" (~(STACK_SIZE - 1))
  341.     );
  342.    
  343.     return v;
  344. }
  345.  
  346. /** Return current IP address */
  347. static inline uintptr_t * get_ip()
  348. {
  349.     uintptr_t *ip;
  350.    
  351.     asm volatile (
  352.         "mov %%eip, %[ip]"
  353.         : [ip] "=r" (ip)
  354.     );
  355.    
  356.     return ip;
  357. }
  358.  
  359. /** Invalidate TLB Entry.
  360.  *
  361.  * @param addr Address on a page whose TLB entry is to be invalidated.
  362.  *
  363.  */
  364. static inline void invlpg(uintptr_t addr)
  365. {
  366.     asm volatile (
  367.         "invlpg %[addr]\n"
  368.         :: [addr] "m" (*(unative_t *) addr)
  369.     );
  370. }
  371.  
  372. /** Load GDTR register from memory.
  373.  *
  374.  * @param gdtr_reg Address of memory from where to load GDTR.
  375.  *
  376.  */
  377. static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
  378. {
  379.     asm volatile (
  380.         "lgdtl %[gdtr_reg]\n"
  381.         :: [gdtr_reg] "m" (*gdtr_reg)
  382.     );
  383. }
  384.  
  385. /** Store GDTR register to memory.
  386.  *
  387.  * @param gdtr_reg Address of memory to where to load GDTR.
  388.  *
  389.  */
  390. static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
  391. {
  392.     asm volatile (
  393.         "sgdtl %[gdtr_reg]\n"
  394.         :: [gdtr_reg] "m" (*gdtr_reg)
  395.     );
  396. }
  397.  
  398. /** Load IDTR register from memory.
  399.  *
  400.  * @param idtr_reg Address of memory from where to load IDTR.
  401.  *
  402.  */
  403. static inline void idtr_load(ptr_16_32_t *idtr_reg)
  404. {
  405.     asm volatile (
  406.         "lidtl %[idtr_reg]\n"
  407.         :: [idtr_reg] "m" (*idtr_reg)
  408.     );
  409. }
  410.  
  411. /** Load TR from descriptor table.
  412.  *
  413.  * @param sel Selector specifying descriptor of TSS segment.
  414.  *
  415.  */
  416. static inline void tr_load(uint16_t sel)
  417. {
  418.     asm volatile (
  419.         "ltr %[sel]"
  420.         :: [sel] "r" (sel)
  421.     );
  422. }
  423.  
  424. #endif
  425.  
  426. /** @}
  427.  */
  428.