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  1. /*
  2.  * Copyright (c) 2001-2004 Jakub Jermar
  3.  * Copyright (c) 2005 Sergey Bondari
  4.  * Copyright (c) 2006 Martin Decky
  5.  * All rights reserved.
  6.  *
  7.  * Redistribution and use in source and binary forms, with or without
  8.  * modification, are permitted provided that the following conditions
  9.  * are met:
  10.  *
  11.  * - Redistributions of source code must retain the above copyright
  12.  *   notice, this list of conditions and the following disclaimer.
  13.  * - Redistributions in binary form must reproduce the above copyright
  14.  *   notice, this list of conditions and the following disclaimer in the
  15.  *   documentation and/or other materials provided with the distribution.
  16.  * - The name of the author may not be used to endorse or promote products
  17.  *   derived from this software without specific prior written permission.
  18.  *
  19.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  20.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  21.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  22.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  23.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  24.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  25.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  26.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  28.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29.  */
  30.  
  31. /** @addtogroup ia32xen
  32.  * @{
  33.  */
  34. /** @file
  35.  */
  36.  
  37. #ifndef KERN_ia32xen_ASM_H_
  38. #define KERN_ia32xen_ASM_H_
  39.  
  40. #include <arch/pm.h>
  41. #include <arch/types.h>
  42. #include <arch/barrier.h>
  43. #include <config.h>
  44.  
  45. extern void enable_l_apic_in_msr(void);
  46.  
  47.  
  48. extern void asm_delay_loop(uint32_t t);
  49. extern void asm_fake_loop(uint32_t t);
  50.  
  51.  
  52. /** Halt CPU
  53.  *
  54.  * Halt the current CPU until interrupt event.
  55.  */
  56. #define cpu_halt() ((void) 0)
  57. #define cpu_sleep() ((void) 0)
  58.  
  59. #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
  60.     { \
  61.     unative_t res; \
  62.     asm volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
  63.     return res; \
  64.     }
  65.  
  66. #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
  67.     { \
  68.     asm volatile ("movl %0, %%" #reg : : "r" (regn)); \
  69.     }
  70.  
  71. GEN_READ_REG(cr0);
  72. GEN_READ_REG(cr2);
  73.  
  74. GEN_READ_REG(dr0);
  75. GEN_READ_REG(dr1);
  76. GEN_READ_REG(dr2);
  77. GEN_READ_REG(dr3);
  78. GEN_READ_REG(dr6);
  79. GEN_READ_REG(dr7);
  80.  
  81. GEN_WRITE_REG(dr0);
  82. GEN_WRITE_REG(dr1);
  83. GEN_WRITE_REG(dr2);
  84. GEN_WRITE_REG(dr3);
  85. GEN_WRITE_REG(dr6);
  86. GEN_WRITE_REG(dr7);
  87.  
  88. /** Byte to port
  89.  *
  90.  * Output byte to port
  91.  *
  92.  * @param port Port to write to
  93.  * @param val Value to write
  94.  */
  95. static inline void outb(uint16_t port, uint8_t val) { asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
  96.  
  97. /** Word to port
  98.  *
  99.  * Output word to port
  100.  *
  101.  * @param port Port to write to
  102.  * @param val Value to write
  103.  */
  104. static inline void outw(uint16_t port, uint16_t val) { asm volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
  105.  
  106. /** Double word to port
  107.  *
  108.  * Output double word to port
  109.  *
  110.  * @param port Port to write to
  111.  * @param val Value to write
  112.  */
  113. static inline void outl(uint16_t port, uint32_t val) { asm volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
  114.  
  115. /** Byte from port
  116.  *
  117.  * Get byte from port
  118.  *
  119.  * @param port Port to read from
  120.  * @return Value read
  121.  */
  122. static inline uint8_t inb(uint16_t port) { uint8_t val; asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
  123.  
  124. /** Word from port
  125.  *
  126.  * Get word from port
  127.  *
  128.  * @param port Port to read from
  129.  * @return Value read
  130.  */
  131. static inline uint16_t inw(uint16_t port) { uint16_t val; asm volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
  132.  
  133. /** Double word from port
  134.  *
  135.  * Get double word from port
  136.  *
  137.  * @param port Port to read from
  138.  * @return Value read
  139.  */
  140. static inline uint32_t inl(uint16_t port) { uint32_t val; asm volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
  141.  
  142. /** Enable interrupts.
  143.  *
  144.  * Enable interrupts and return previous
  145.  * value of EFLAGS.
  146.  *
  147.  * @return Old interrupt priority level.
  148.  */
  149. static inline ipl_t interrupts_enable(void)
  150. {
  151.     // FIXME SMP
  152.    
  153.     ipl_t v = shared_info.vcpu_info[0].evtchn_upcall_mask;
  154.     write_barrier();
  155.     shared_info.vcpu_info[0].evtchn_upcall_mask = 0;
  156.     write_barrier();
  157.     if (shared_info.vcpu_info[0].evtchn_upcall_pending)
  158.         force_evtchn_callback();
  159.    
  160.     return v;
  161. }
  162.  
  163. /** Disable interrupts.
  164.  *
  165.  * Disable interrupts and return previous
  166.  * value of EFLAGS.
  167.  *
  168.  * @return Old interrupt priority level.
  169.  */
  170. static inline ipl_t interrupts_disable(void)
  171. {
  172.     // FIXME SMP
  173.    
  174.     ipl_t v = shared_info.vcpu_info[0].evtchn_upcall_mask;
  175.     shared_info.vcpu_info[0].evtchn_upcall_mask = 1;
  176.     write_barrier();
  177.    
  178.     return v;
  179. }
  180.  
  181. /** Restore interrupt priority level.
  182.  *
  183.  * Restore EFLAGS.
  184.  *
  185.  * @param ipl Saved interrupt priority level.
  186.  */
  187. static inline void interrupts_restore(ipl_t ipl)
  188. {
  189.     if (ipl == 0)
  190.         interrupts_enable();
  191.     else
  192.         interrupts_disable();
  193. }
  194.  
  195. /** Return interrupt priority level.
  196.  *
  197.  * @return EFLAFS.
  198.  */
  199. static inline ipl_t interrupts_read(void)
  200. {
  201.     // FIXME SMP
  202.    
  203.     return shared_info.vcpu_info[0].evtchn_upcall_mask;
  204. }
  205.  
  206. /** Return base address of current stack
  207.  *
  208.  * Return the base address of the current stack.
  209.  * The stack is assumed to be STACK_SIZE bytes long.
  210.  * The stack must start on page boundary.
  211.  */
  212. static inline uintptr_t get_stack_base(void)
  213. {
  214.     uintptr_t v;
  215.    
  216.     asm volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
  217.    
  218.     return v;
  219. }
  220.  
  221. /** Return current IP address */
  222. static inline uintptr_t * get_ip()
  223. {
  224.     uintptr_t *ip;
  225.  
  226.     asm volatile (
  227.         "mov %%eip, %0"
  228.         : "=r" (ip)
  229.         );
  230.     return ip;
  231. }
  232.  
  233. /** Invalidate TLB Entry.
  234.  *
  235.  * @param addr Address on a page whose TLB entry is to be invalidated.
  236.  */
  237. static inline void invlpg(uintptr_t addr)
  238. {
  239.     asm volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr));
  240. }
  241.  
  242. /** Load GDTR register from memory.
  243.  *
  244.  * @param gdtr_reg Address of memory from where to load GDTR.
  245.  */
  246. static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
  247. {
  248.     asm volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));
  249. }
  250.  
  251. /** Store GDTR register to memory.
  252.  *
  253.  * @param gdtr_reg Address of memory to where to load GDTR.
  254.  */
  255. static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
  256. {
  257.     asm volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));
  258. }
  259.  
  260. /** Load TR from descriptor table.
  261.  *
  262.  * @param sel Selector specifying descriptor of TSS segment.
  263.  */
  264. static inline void tr_load(uint16_t sel)
  265. {
  266.     asm volatile ("ltr %0" : : "r" (sel));
  267. }
  268.  
  269. #endif
  270.  
  271. /** @}
  272.  */
  273.