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  1. /*
  2.  * Copyright (C) 2005 Ondrej Palkovsky
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup amd64
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #include <arch.h>
  36.  
  37. #include <arch/types.h>
  38.  
  39. #include <config.h>
  40.  
  41. #include <proc/thread.h>
  42. #include <arch/drivers/ega.h>
  43. #include <arch/drivers/vesa.h>
  44. #include <genarch/kbd/i8042.h>
  45. #include <arch/drivers/i8254.h>
  46. #include <arch/drivers/i8259.h>
  47.  
  48. #ifdef CONFIG_SMP
  49. #include <arch/smp/apic.h>
  50. #endif
  51.  
  52. #include <arch/bios/bios.h>
  53. #include <arch/mm/memory_init.h>
  54. #include <arch/cpu.h>
  55. #include <print.h>
  56. #include <arch/cpuid.h>
  57. #include <genarch/acpi/acpi.h>
  58. #include <panic.h>
  59. #include <interrupt.h>
  60. #include <arch/syscall.h>
  61. #include <arch/debugger.h>
  62. #include <syscall/syscall.h>
  63. #include <console/console.h>
  64. #include <ddi/irq.h>
  65. #include <ddi/device.h>
  66.  
  67.  
  68. /** Disable I/O on non-privileged levels
  69.  *
  70.  * Clean IOPL(12,13) and NT(14) flags in EFLAGS register
  71.  */
  72. static void clean_IOPL_NT_flags(void)
  73. {
  74.     asm
  75.     (
  76.         "pushfq;"
  77.         "pop %%rax;"
  78.         "and $~(0x7000),%%rax;"
  79.         "pushq %%rax;"
  80.         "popfq;"
  81.         :
  82.         :
  83.         :"%rax"
  84.     );
  85. }
  86.  
  87. /** Disable alignment check
  88.  *
  89.  * Clean AM(18) flag in CR0 register
  90.  */
  91. static void clean_AM_flag(void)
  92. {
  93.     asm
  94.     (
  95.         "mov %%cr0,%%rax;"
  96.         "and $~(0x40000),%%rax;"
  97.         "mov %%rax,%%cr0;"
  98.         :
  99.         :
  100.         :"%rax"
  101.     );
  102. }
  103.  
  104. void arch_pre_mm_init(void)
  105. {
  106.     struct cpu_info cpuid_s;
  107.  
  108.     cpuid(AMD_CPUID_EXTENDED,&cpuid_s);
  109.     if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE)))
  110.         panic("Processor does not support No-execute pages.\n");
  111.  
  112.     cpuid(INTEL_CPUID_STANDARD,&cpuid_s);
  113.     if (! (cpuid_s.cpuid_edx & (1<<INTEL_FXSAVE)))
  114.         panic("Processor does not support FXSAVE/FXRESTORE.\n");
  115.    
  116.     if (! (cpuid_s.cpuid_edx & (1<<INTEL_SSE2)))
  117.         panic("Processor does not support SSE2 instructions.\n");
  118.  
  119.     /* Enable No-execute pages */
  120.     set_efer_flag(AMD_NXE_FLAG);
  121.     /* Enable FPU */
  122.     cpu_setup_fpu();
  123.  
  124.     /* Initialize segmentation */
  125.     pm_init();
  126.  
  127.         /* Disable I/O on nonprivileged levels
  128.      * clear the NT(nested-thread) flag
  129.      */
  130.     clean_IOPL_NT_flags();
  131.     /* Disable alignment check */
  132.     clean_AM_flag();
  133.  
  134.     if (config.cpu_active == 1) {
  135.         interrupt_init();
  136.         bios_init();
  137.        
  138.         /* PIC */
  139.         i8259_init();
  140.     }
  141. }
  142.  
  143. void arch_post_mm_init(void)
  144. {
  145.     if (config.cpu_active == 1) {
  146.         /* Initialize IRQ routing */
  147.         irq_init(IRQ_COUNT, IRQ_COUNT);
  148.        
  149.         /* hard clock */
  150.         i8254_init();
  151.  
  152. #ifdef CONFIG_FB
  153.         if (vesa_present())
  154.             vesa_init();
  155.         else
  156. #endif
  157.             ega_init(); /* video */
  158.        
  159.         /* Enable debugger */
  160.         debugger_init();
  161.         /* Merge all memory zones to 1 big zone */
  162.         zone_merge_all();
  163.     }
  164.     /* Setup fast SYSCALL/SYSRET */
  165.     syscall_setup_cpu();
  166.    
  167. }
  168.  
  169. void arch_post_cpu_init()
  170. {
  171. #ifdef CONFIG_SMP
  172.     if (config.cpu_active > 1) {
  173.         l_apic_init();
  174.         l_apic_debug();
  175.     }
  176. #endif
  177. }
  178.  
  179. void arch_pre_smp_init(void)
  180. {
  181.     if (config.cpu_active == 1) {
  182.         memory_print_map();
  183.        
  184.         #ifdef CONFIG_SMP
  185.         acpi_init();
  186.         #endif /* CONFIG_SMP */
  187.     }
  188. }
  189.  
  190. void arch_post_smp_init(void)
  191. {
  192.     /* keyboard controller */
  193.     i8042_init(device_assign_devno(), IRQ_KBD, device_assign_devno(), IRQ_MOUSE);
  194. }
  195.  
  196. void calibrate_delay_loop(void)
  197. {
  198.     i8254_calibrate_delay_loop();
  199.     if (config.cpu_active == 1) {
  200.         /*
  201.          * This has to be done only on UP.
  202.          * On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.
  203.          */
  204.         i8254_normal_operation();
  205.     }
  206. }
  207.  
  208. /** Set thread-local-storage pointer
  209.  *
  210.  * TLS pointer is set in FS register. Unfortunately the 64-bit
  211.  * part can be set only in CPL0 mode.
  212.  *
  213.  * The specs say, that on %fs:0 there is stored contents of %fs register,
  214.  * we need not to go to CPL0 to read it.
  215.  */
  216. unative_t sys_tls_set(unative_t addr)
  217. {
  218.     THREAD->arch.tls = addr;
  219.     write_msr(AMD_MSR_FS, addr);
  220.     return 0;
  221. }
  222.  
  223. /** Acquire console back for kernel
  224.  *
  225.  */
  226. void arch_grab_console(void)
  227. {
  228.     i8042_grab();
  229. }
  230. /** Return console to userspace
  231.  *
  232.  */
  233. void arch_release_console(void)
  234. {
  235.     i8042_release();
  236. }
  237.  
  238. /** @}
  239.  */
  240.