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  1. /*
  2.  * Copyright (C) 2005 Martin Decky
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup ppc32  
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #ifndef __ppc32_REGNAME_H__
  36. #define __ppc32_REGNAME_H__
  37.  
  38. /* Condition Register Bit Fields */
  39. #define cr0 0
  40. #define cr1 1
  41. #define cr2 2
  42. #define cr3 3
  43. #define cr4 4
  44. #define cr5 5
  45. #define cr6 6
  46. #define cr7 7
  47.  
  48. /* General Purpose Registers (GPRs) */
  49. #define r0  0
  50. #define r1  1
  51. #define r2  2
  52. #define r3  3
  53. #define r4  4
  54. #define r5  5
  55. #define r6  6
  56. #define r7  7
  57. #define r8  8
  58. #define r9  9
  59. #define r10 10
  60. #define r11 11
  61. #define r12 12
  62. #define r13 13
  63. #define r14 14
  64. #define r15 15
  65. #define r16 16
  66. #define r17 17
  67. #define r18 18
  68. #define r19 19
  69. #define r20 20
  70. #define r21 21
  71. #define r22 22
  72. #define r23 23
  73. #define r24 24
  74. #define r25 25
  75. #define r26 26
  76. #define r27 27
  77. #define r28 28
  78. #define r29 29
  79. #define r30 30
  80. #define r31 31
  81.  
  82. /* GPR Aliases */
  83. #define sp  1
  84.  
  85. /* Floating Point Registers (FPRs) */
  86. #define fr0     0
  87. #define fr1     1
  88. #define fr2     2
  89. #define fr3     3
  90. #define fr4     4
  91. #define fr5     5
  92. #define fr6     6
  93. #define fr7     7
  94. #define fr8     8
  95. #define fr9     9
  96. #define fr10    10
  97. #define fr11    11
  98. #define fr12    12
  99. #define fr13    13
  100. #define fr14    14
  101. #define fr15    15
  102. #define fr16    16
  103. #define fr17    17
  104. #define fr18    18
  105. #define fr19    19
  106. #define fr20    20
  107. #define fr21    21
  108. #define fr22    22
  109. #define fr23    23
  110. #define fr24    24
  111. #define fr25    25
  112. #define fr26    26
  113. #define fr27    27
  114. #define fr28    28
  115. #define fr29    29
  116. #define fr30    30
  117. #define fr31    31
  118.  
  119. #define vr0     0
  120. #define vr1     1
  121. #define vr2     2
  122. #define vr3     3
  123. #define vr4     4
  124. #define vr5     5
  125. #define vr6     6
  126. #define vr7     7
  127. #define vr8     8
  128. #define vr9     9
  129. #define vr10    10
  130. #define vr11    11
  131. #define vr12    12
  132. #define vr13    13
  133. #define vr14    14
  134. #define vr15    15
  135. #define vr16    16
  136. #define vr17    17
  137. #define vr18    18
  138. #define vr19    19
  139. #define vr20    20
  140. #define vr21    21
  141. #define vr22    22
  142. #define vr23    23
  143. #define vr24    24
  144. #define vr25    25
  145. #define vr26    26
  146. #define vr27    27
  147. #define vr28    28
  148. #define vr29    29
  149. #define vr30    30
  150. #define vr31    31
  151.  
  152. #define evr0    0
  153. #define evr1    1
  154. #define evr2    2
  155. #define evr3    3
  156. #define evr4    4
  157. #define evr5    5
  158. #define evr6    6
  159. #define evr7    7
  160. #define evr8    8
  161. #define evr9    9
  162. #define evr10   10
  163. #define evr11   11
  164. #define evr12   12
  165. #define evr13   13
  166. #define evr14   14
  167. #define evr15   15
  168. #define evr16   16
  169. #define evr17   17
  170. #define evr18   18
  171. #define evr19   19
  172. #define evr20   20
  173. #define evr21   21
  174. #define evr22   22
  175. #define evr23   23
  176. #define evr24   24
  177. #define evr25   25
  178. #define evr26   26
  179. #define evr27   27
  180. #define evr28   28
  181. #define evr29   29
  182. #define evr30   30
  183. #define evr31   31
  184.  
  185. /* Special Purpose Registers (SPRs) */
  186. #define xer     1
  187. #define lr      8
  188. #define ctr     9
  189. #define dec     22
  190. #define sdr1    25
  191. #define srr0    26
  192. #define srr1    27
  193. #define sprg0   272
  194. #define sprg1   273
  195. #define sprg2   274
  196. #define sprg3   275
  197. #define prv     287
  198. #define ibat0u  528
  199. #define ibat0l  529
  200. #define ibat1u  530
  201. #define ibat1l  531
  202. #define ibat2u  532
  203. #define ibat2l  533
  204. #define ibat3u  534
  205. #define ibat3l  535
  206. #define dbat0u  536
  207. #define dbat0l  537
  208. #define dbat1u  538
  209. #define dbat1l  539
  210. #define dbat2u  540
  211. #define dbat2l  541
  212. #define dbat3u  542
  213. #define dbat3l  543
  214. #define hid0    1008
  215.  
  216. /* MSR bits */
  217. #define msr_ir  (1 << 4)
  218. #define msr_dr  (1 << 5)
  219. #define msr_pr  (1 << 14)
  220. #define msr_ee  (1 << 15)
  221.  
  222. /* HID0 bits */
  223. #define hid0_ice    (1 << 15)
  224. #define hid0_dce    (1 << 14)
  225. #define hid0_icfi   (1 << 11)
  226. #define hid0_dci    (1 << 10)
  227.  
  228. #endif
  229.  
  230. /** @}
  231.  */
  232.