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  1. /*
  2.  * Copyright (C) 2005 Ondrej Palkovsky
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #ifndef __mips32_ATOMIC_H__
  30. #define __mips32_ATOMIC_H__
  31.  
  32. #define atomic_inc(x)   (a_add(x,1))
  33. #define atomic_dec(x)   (a_sub(x,1))
  34.  
  35. /*
  36.  * Atomic addition
  37.  *
  38.  * This case is harder, and we have to use the special LL and SC operations
  39.  * to achieve atomicity. The instructions are similar to LW (load) and SW
  40.  * (store), except that the LL (load-linked) instruction loads the address
  41.  * of the variable to a special register and if another process writes to
  42.  * the same location, the SC (store-conditional) instruction fails.
  43.  */
  44. static inline int a_add( volatile int *val, int i)
  45. {
  46.     int tmp, tmp2;
  47.  
  48.     asm volatile (
  49.         "   .set    push\n"
  50.         "   .set    noreorder\n"
  51.         "   nop\n"
  52.         "1:\n"
  53.         "   ll  %0, %1\n"
  54.         "   addu    %0, %0, %3\n"
  55.         "       move    %2, %0\n"
  56.         "   sc  %0, %1\n"
  57.         "   beq %0, 0x0, 1b\n"
  58.         "   move    %0, %2\n"
  59.         "   .set    pop\n"
  60.         : "=&r" (tmp), "=o" (*val), "=r" (tmp2)
  61.         : "r" (i)
  62.         );
  63.     return tmp;
  64. }
  65.  
  66.  
  67. /*
  68.  * Atomic subtraction
  69.  *
  70.  * Implemented in the same manner as a_add, except we substract the value.
  71.  */
  72. static inline int a_sub( volatile int *val, int i)
  73.  
  74. {
  75.     int tmp, tmp2;
  76.  
  77.     asm volatile (
  78.         "   .set    push\n"
  79.         "   .set    noreorder\n"
  80.         "   nop\n"
  81.         "1:\n"
  82.         "   ll  %0, %1\n"
  83.         "   subu    %0, %0, %3\n"
  84.         "       move    %2, %0\n"
  85.         "   sc  %0, %1\n"
  86.         "   beq %0, 0x0, 1b\n"
  87.         "       move    %0, %2\n"
  88.         "   .set    pop\n"
  89.         : "=&r" (tmp), "=o" (*val), "=r" (tmp2)
  90.         : "r" (i)
  91.         );
  92.     return tmp;
  93. }
  94.  
  95.  
  96. #endif
  97.