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  1. /*
  2.  * Copyright (c) 2006 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup sparc64mm
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #include <arch/mm/as.h>
  36. #include <arch/mm/pagesize.h>
  37. #include <arch/mm/tlb.h>
  38. #include <genarch/mm/page_ht.h>
  39. #include <genarch/mm/asid_fifo.h>
  40. #include <debug.h>
  41. #include <config.h>
  42.  
  43. #ifdef CONFIG_TSB
  44. #include <arch/mm/tsb.h>
  45. #include <arch/memstr.h>
  46. #include <arch/asm.h>
  47. #include <mm/frame.h>
  48. #include <bitops.h>
  49. #include <macros.h>
  50. #endif /* CONFIG_TSB */
  51.  
  52. /** Architecture dependent address space init. */
  53. void as_arch_init(void)
  54. {
  55.     if (config.cpu_active == 1) {
  56.         as_operations = &as_ht_operations;
  57.         asid_fifo_init();
  58.     }
  59. }
  60.  
  61. int as_constructor_arch(as_t *as, int flags)
  62. {
  63. #ifdef CONFIG_TSB
  64.     /*
  65.      * The order must be calculated with respect to the emulated
  66.      * 16K page size.
  67.      */
  68.     int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
  69.         sizeof(tsb_entry_t)) >> FRAME_WIDTH);
  70.  
  71.     uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA);
  72.  
  73.     if (!tsb)
  74.         return -1;
  75.  
  76.     as->arch.itsb = (tsb_entry_t *) tsb;
  77.     as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT *
  78.         sizeof(tsb_entry_t));
  79.  
  80.     memsetb(as->arch.itsb,
  81.         (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0);
  82. #endif
  83.     return 0;
  84. }
  85.  
  86. int as_destructor_arch(as_t *as)
  87. {
  88. #ifdef CONFIG_TSB
  89.     /*
  90.      * The count must be calculated with respect to the emualted 16K page
  91.      * size.
  92.      */
  93.     count_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
  94.         sizeof(tsb_entry_t)) >> FRAME_WIDTH;
  95.     frame_free(KA2PA((uintptr_t) as->arch.itsb));
  96.     return cnt;
  97. #else
  98.     return 0;
  99. #endif
  100. }
  101.  
  102. int as_create_arch(as_t *as, int flags)
  103. {
  104. #ifdef CONFIG_TSB
  105.     tsb_invalidate(as, 0, (count_t) -1);
  106. #endif
  107.     return 0;
  108. }
  109.  
  110. /** Perform sparc64-specific tasks when an address space becomes active on the
  111.  * processor.
  112.  *
  113.  * Install ASID and map TSBs.
  114.  *
  115.  * @param as Address space.
  116.  */
  117. void as_install_arch(as_t *as)
  118. {
  119.     tlb_context_reg_t ctx;
  120.    
  121.     /*
  122.      * Note that we don't and may not lock the address space. That's ok
  123.      * since we only read members that are currently read-only.
  124.      *
  125.      * Moreover, the as->asid is protected by asidlock, which is being held.
  126.      */
  127.    
  128.     /*
  129.      * Write ASID to secondary context register. The primary context
  130.      * register has to be set from TL>0 so it will be filled from the
  131.      * secondary context register from the TL=1 code just before switch to
  132.      * userspace.
  133.      */
  134.     ctx.v = 0;
  135.     ctx.context = as->asid;
  136.     mmu_secondary_context_write(ctx.v);
  137.  
  138. #ifdef CONFIG_TSB  
  139.     uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
  140.  
  141.     ASSERT(as->arch.itsb && as->arch.dtsb);
  142.  
  143.     uintptr_t tsb = (uintptr_t) as->arch.itsb;
  144.        
  145.     if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
  146.         /*
  147.          * TSBs were allocated from memory not covered
  148.          * by the locked 4M kernel DTLB entry. We need
  149.          * to map both TSBs explicitly.
  150.          */
  151.         dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
  152.         dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true);
  153.     }
  154.        
  155.     /*
  156.      * Setup TSB Base registers.
  157.      */
  158.     tsb_base_reg_t tsb_base;
  159.        
  160.     tsb_base.value = 0;
  161.     tsb_base.size = TSB_SIZE;
  162.     tsb_base.split = 0;
  163.  
  164.     tsb_base.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH;
  165.     itsb_base_write(tsb_base.value);
  166.     tsb_base.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH;
  167.     dtsb_base_write(tsb_base.value);
  168.    
  169. #if defined (US3)
  170.     /*
  171.      * Clear the extension registers.
  172.      * In HelenOS, primary and secondary context registers contain
  173.      * equal values and kernel misses (context 0, ie. the nucleus context)
  174.      * are excluded from the TSB miss handler, so it makes no sense
  175.      * to have separate TSBs for primary, secondary and nucleus contexts.
  176.      * Clearing the extension registers will ensure that the value of the
  177.      * TSB Base register will be used as an address of TSB, making the code
  178.      * compatible with the US port.
  179.      */
  180.     itsb_primary_extension_write(0);
  181.     itsb_nucleus_extension_write(0);
  182.     dtsb_primary_extension_write(0);
  183.     dtsb_secondary_extension_write(0);
  184.     dtsb_nucleus_extension_write(0);
  185. #endif
  186. #endif
  187. }
  188.  
  189. /** Perform sparc64-specific tasks when an address space is removed from the
  190.  * processor.
  191.  *
  192.  * Demap TSBs.
  193.  *
  194.  * @param as Address space.
  195.  */
  196. void as_deinstall_arch(as_t *as)
  197. {
  198.  
  199.     /*
  200.      * Note that we don't and may not lock the address space. That's ok
  201.      * since we only read members that are currently read-only.
  202.      *
  203.      * Moreover, the as->asid is protected by asidlock, which is being held.
  204.      */
  205.  
  206. #ifdef CONFIG_TSB
  207.     uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
  208.  
  209.     ASSERT(as->arch.itsb && as->arch.dtsb);
  210.  
  211.     uintptr_t tsb = (uintptr_t) as->arch.itsb;
  212.        
  213.     if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
  214.         /*
  215.          * TSBs were allocated from memory not covered
  216.          * by the locked 4M kernel DTLB entry. We need
  217.          * to demap the entry installed by as_install_arch().
  218.          */
  219.         dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
  220.     }
  221. #endif
  222. }
  223.  
  224. /** @}
  225.  */
  226.