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  1. /*
  2.  * Copyright (c) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup sparc64interrupt
  30.  * @{
  31.  */
  32. /**
  33.  * @file
  34.  * @brief This file contains interrupt vector trap handler.
  35.  */
  36.  
  37. #ifndef KERN_sparc64_TRAP_INTERRUPT_H_
  38. #define KERN_sparc64_TRAP_INTERRUPT_H_
  39.  
  40. #include <arch/trap/trap_table.h>
  41. #include <arch/stack.h>
  42.  
  43. /* IMAP register bits */
  44. #define IGN_MASK    0x7c0
  45. #define INO_MASK    0x1f
  46. #define IMAP_V_MASK (1ULL << 31)
  47.  
  48. #define IGN_SHIFT   6
  49.  
  50.  
  51. /* Interrupt ASI registers. */
  52. #define ASI_INTR_W          0x77
  53. #define ASI_INTR_DISPATCH_STATUS    0x48
  54. #define ASI_INTR_R          0x7f
  55. #define ASI_INTR_RECEIVE        0x49
  56.  
  57. /* VA's used with ASI_UDB_INTR_W register. */
  58. #if defined (US)
  59. #define ASI_UDB_INTR_W_DATA_0   0x40
  60. #define ASI_UDB_INTR_W_DATA_1   0x50
  61. #define ASI_UDB_INTR_W_DATA_2   0x60
  62. #elif defined (US3)
  63. #define VA_INTR_W_DATA_0    0x40
  64. #define VA_INTR_W_DATA_1    0x48
  65. #define VA_INTR_W_DATA_2    0x50
  66. #define VA_INTR_W_DATA_3    0x58
  67. #define VA_INTR_W_DATA_4    0x60
  68. #define VA_INTR_W_DATA_5    0x68
  69. #define VA_INTR_W_DATA_6    0x80
  70. #define VA_INTR_W_DATA_7    0x88
  71. #endif
  72. #define VA_INTR_W_DISPATCH  0x70
  73.  
  74. /* VA's used with ASI_UDB_INTR_R register. */
  75. #if defined(US)
  76. #define ASI_UDB_INTR_R_DATA_0   0x40
  77. #define ASI_UDB_INTR_R_DATA_1   0x50
  78. #define ASI_UDB_INTR_R_DATA_2   0x60
  79. #elif defined (US3)
  80. #define VA_INTR_R_DATA_0    0x40
  81. #define VA_INTR_R_DATA_1    0x48
  82. #define VA_INTR_R_DATA_2    0x50
  83. #define VA_INTR_R_DATA_3    0x58
  84. #define VA_INTR_R_DATA_4    0x60
  85. #define VA_INTR_R_DATA_5    0x68
  86. #define VA_INTR_R_DATA_6    0x80
  87. #define VA_INTR_R_DATA_7    0x88
  88. #endif
  89.  
  90. /* Shifts in the Interrupt Vector Dispatch virtual address. */
  91. #define INTR_VEC_DISPATCH_MID_SHIFT 14
  92.  
  93. /* Bits in the Interrupt Dispatch Status register. */
  94. #define INTR_DISPATCH_STATUS_NACK   0x2
  95. #define INTR_DISPATCH_STATUS_BUSY   0x1
  96.  
  97. #define TT_INTERRUPT_LEVEL_1            0x41
  98. #define TT_INTERRUPT_LEVEL_2            0x42
  99. #define TT_INTERRUPT_LEVEL_3            0x43
  100. #define TT_INTERRUPT_LEVEL_4            0x44
  101. #define TT_INTERRUPT_LEVEL_5            0x45
  102. #define TT_INTERRUPT_LEVEL_6            0x46
  103. #define TT_INTERRUPT_LEVEL_7            0x47
  104. #define TT_INTERRUPT_LEVEL_8            0x48
  105. #define TT_INTERRUPT_LEVEL_9            0x49
  106. #define TT_INTERRUPT_LEVEL_10           0x4a
  107. #define TT_INTERRUPT_LEVEL_11           0x4b
  108. #define TT_INTERRUPT_LEVEL_12           0x4c
  109. #define TT_INTERRUPT_LEVEL_13           0x4d
  110. #define TT_INTERRUPT_LEVEL_14           0x4e
  111. #define TT_INTERRUPT_LEVEL_15           0x4f
  112.  
  113. #define TT_INTERRUPT_VECTOR_TRAP        0x60
  114.  
  115. #define INTERRUPT_LEVEL_N_HANDLER_SIZE      TRAP_TABLE_ENTRY_SIZE
  116. #define INTERRUPT_VECTOR_TRAP_HANDLER_SIZE  TRAP_TABLE_ENTRY_SIZE
  117.  
  118. #ifdef __ASM__
  119. .macro INTERRUPT_LEVEL_N_HANDLER n
  120.     mov \n - 1, %g2
  121.     PREEMPTIBLE_HANDLER exc_dispatch
  122. .endm
  123.  
  124. .macro INTERRUPT_VECTOR_TRAP_HANDLER
  125.     PREEMPTIBLE_HANDLER interrupt
  126. .endm
  127. #endif /* __ASM__ */
  128.  
  129. #ifndef __ASM__
  130.  
  131. #include <arch/interrupt.h>
  132.  
  133. extern void interrupt(int n, istate_t *istate);
  134. #endif /* !def __ASM__ */
  135.  
  136. #endif
  137.  
  138. /** @}
  139.  */
  140.