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  1. /*
  2.  * Copyright (c) 2005 Jakub Jermar
  3.  * Copyright (c) 2008 Pavel Rimsky
  4.  * All rights reserved.
  5.  *
  6.  * Redistribution and use in source and binary forms, with or without
  7.  * modification, are permitted provided that the following conditions
  8.  * are met:
  9.  *
  10.  * - Redistributions of source code must retain the above copyright
  11.  *   notice, this list of conditions and the following disclaimer.
  12.  * - Redistributions in binary form must reproduce the above copyright
  13.  *   notice, this list of conditions and the following disclaimer in the
  14.  *   documentation and/or other materials provided with the distribution.
  15.  * - The name of the author may not be used to endorse or promote products
  16.  *   derived from this software without specific prior written permission.
  17.  *
  18.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28.  */
  29.  
  30. /** @addtogroup sparc64mm  
  31.  * @{
  32.  */
  33. /** @file
  34.  */
  35.  
  36. #ifndef KERN_sparc64_sun4v_TLB_H_
  37. #define KERN_sparc64_sun4v_TLB_H_
  38.  
  39. #define MMU_FSA_ALIGNMENT   64
  40. #define MMU_FSA_SIZE        128
  41.  
  42. #ifndef __ASM__
  43.  
  44. #include <arch/mm/tte.h>
  45. #include <print.h>
  46. #include <arch/mm/mmu.h>
  47. #include <arch/mm/page.h>
  48. #include <arch/asm.h>
  49. #include <arch/barrier.h>
  50. #include <arch/types.h>
  51. #include <arch/register.h>
  52. #include <arch/cpu.h>
  53. #include <arch/sun4v/hypercall.h>
  54.  
  55. /**
  56.  * Structure filled by hypervisor (or directly CPU, if implemented so) when
  57.  * a MMU fault occurs. The structure describes the exact condition which
  58.  * has caused the fault.
  59.  */
  60. typedef struct mmu_fault_status_area {
  61.     uint64_t ift;       /**< Instruction fault type (IFT) */
  62.     uint64_t ifa;       /**< Instruction fault address (IFA) */
  63.     uint64_t ifc;       /**< Instruction fault context (IFC) */
  64.     uint8_t reserved1[0x28];
  65.  
  66.     uint64_t dft;       /**< Data fault type (DFT) */
  67.     uint64_t dfa;       /**< Data fault address (DFA) */
  68.     uint64_t dfc;       /**< Data fault context (DFC) */
  69.     uint8_t reserved2[0x28];
  70. } __attribute__ ((packed)) mmu_fault_status_area_t;
  71.  
  72. #define DTLB_MAX_LOCKED_ENTRIES     8
  73.  
  74. /** Bit width of the TLB-locked portion of kernel address space. */
  75. #define KERNEL_PAGE_WIDTH       22  /* 4M */
  76.  
  77. /*
  78.  * Reading and writing context registers.
  79.  *
  80.  * Note that UltraSPARC Architecture-compatible processors do not require
  81.  * a MEMBAR #Sync, FLUSH, DONE, or RETRY instruction after a store to an
  82.  * MMU register for proper operation.
  83.  *
  84.  */
  85.  
  86. /** Read MMU Primary Context Register.
  87.  *
  88.  * @return  Current value of Primary Context Register.
  89.  */
  90. static inline uint64_t mmu_primary_context_read(void)
  91. {
  92.     return asi_u64_read(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG);
  93. }
  94.  
  95. /** Write MMU Primary Context Register.
  96.  *
  97.  * @param v New value of Primary Context Register.
  98.  */
  99. static inline void mmu_primary_context_write(uint64_t v)
  100. {
  101.     asi_u64_write(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG, v);
  102. }
  103.  
  104. /** Read MMU Secondary Context Register.
  105.  *
  106.  * @return  Current value of Secondary Context Register.
  107.  */
  108. static inline uint64_t mmu_secondary_context_read(void)
  109. {
  110.     return asi_u64_read(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG);
  111. }
  112.  
  113. /** Write MMU Secondary Context Register.
  114.  *
  115.  * @param v New value of Secondary Context Register.
  116.  */
  117. static inline void mmu_secondary_context_write(uint64_t v)
  118. {
  119.     asi_u64_write(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG, v);
  120. }
  121.  
  122. /**
  123.  * Demaps all mappings in a context.
  124.  *
  125.  * @param context   number of the context
  126.  * @param mmu_flag  MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both
  127.  */
  128. static inline void mmu_demap_ctx(int context, int mmu_flag) {
  129.     __hypercall_fast4(MMU_DEMAP_CTX, 0, 0, context, mmu_flag);
  130. }
  131.  
  132. /**
  133.  * Demaps given page.
  134.  *
  135.  * @param vaddr     VA of the page to be demapped
  136.  * @param context   number of the context
  137.  * @param mmu_flag  MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both
  138.  */
  139. static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag) {
  140.     __hypercall_fast5(MMU_DEMAP_PAGE, 0, 0, vaddr, context, mmu_flag);
  141. }
  142.  
  143. extern void fast_instruction_access_mmu_miss(unative_t, istate_t *);
  144. extern void fast_data_access_mmu_miss(unative_t, istate_t *);
  145. extern void fast_data_access_protection(unative_t, istate_t *);
  146.  
  147. extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);
  148.  
  149. extern void describe_dmmu_fault(void);
  150.  
  151. #endif /* !def __ASM__ */
  152.  
  153. #endif
  154.  
  155. /** @}
  156.  */
  157.