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  1. /*
  2.  * Copyright (c) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup sparc64mm  
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #ifndef KERN_sparc64_sun4u_TLB_H_
  36. #define KERN_sparc64_sun4u_TLB_H_
  37.  
  38. #if defined (US)
  39. #define ITLB_ENTRY_COUNT        64
  40. #define DTLB_ENTRY_COUNT        64
  41. #define DTLB_MAX_LOCKED_ENTRIES     DTLB_ENTRY_COUNT
  42. #endif
  43.  
  44. /** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */
  45. #if defined (US3)
  46. #define DTLB_MAX_LOCKED_ENTRIES     16
  47. #endif
  48.  
  49. /** Bit width of the TLB-locked portion of kernel address space. */
  50. #define KERNEL_PAGE_WIDTH       22  /* 4M */
  51.  
  52. /* TLB Demap Operation types. */
  53. #define TLB_DEMAP_PAGE      0
  54. #define TLB_DEMAP_CONTEXT   1
  55. #if defined (US3)
  56. #define TLB_DEMAP_ALL       2
  57. #endif
  58.  
  59. #define TLB_DEMAP_TYPE_SHIFT    6
  60.  
  61. /* TLB Demap Operation Context register encodings. */
  62. #define TLB_DEMAP_PRIMARY   0
  63. #define TLB_DEMAP_SECONDARY 1
  64. #define TLB_DEMAP_NUCLEUS   2
  65.  
  66. /* There are more TLBs in one MMU in US3, their codes are defined here. */
  67. #if defined (US3)
  68. /* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */
  69. #define TLB_DSMALL  0
  70. #define TLB_DBIG_0  2
  71. #define TLB_DBIG_1  3
  72.    
  73. /* I-MMU: one small (16-entry) TLB and one big TLB */
  74. #define TLB_ISMALL  0
  75. #define TLB_IBIG    2
  76. #endif
  77.  
  78. #define TLB_DEMAP_CONTEXT_SHIFT 4
  79.  
  80. /* TLB Tag Access shifts */
  81. #define TLB_TAG_ACCESS_CONTEXT_SHIFT    0
  82. #define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1)
  83. #define TLB_TAG_ACCESS_VPN_SHIFT    13
  84.  
  85. #ifndef __ASM__
  86.  
  87. #include <arch/mm/sun4u/tte.h>
  88. #include <arch/mm/sun4u/mmu.h>
  89. #include <arch/mm/page.h>
  90. #include <arch/asm.h>
  91. #include <arch/barrier.h>
  92. #include <arch/types.h>
  93. #include <arch/register.h>
  94. #include <arch/cpu.h>
  95.  
  96. union tlb_context_reg {
  97.     uint64_t v;
  98.     struct {
  99.         unsigned long : 51;
  100.         unsigned context : 13;      /**< Context/ASID. */
  101.     } __attribute__ ((packed));
  102. };
  103. typedef union tlb_context_reg tlb_context_reg_t;
  104.  
  105. /** I-/D-TLB Data In/Access Register type. */
  106. typedef tte_data_t tlb_data_t;
  107.  
  108. /** I-/D-TLB Data Access Address in Alternate Space. */
  109.  
  110. #if defined (US)
  111.  
  112. union tlb_data_access_addr {
  113.     uint64_t value;
  114.     struct {
  115.         uint64_t : 55;
  116.         unsigned tlb_entry : 6;
  117.         unsigned : 3;
  118.     } __attribute__ ((packed));
  119. };
  120. typedef union tlb_data_access_addr dtlb_data_access_addr_t;
  121. typedef union tlb_data_access_addr dtlb_tag_read_addr_t;
  122. typedef union tlb_data_access_addr itlb_data_access_addr_t;
  123. typedef union tlb_data_access_addr itlb_tag_read_addr_t;
  124.  
  125. #elif defined (US3)
  126.  
  127. /*
  128.  * In US3, I-MMU and D-MMU have different formats of the data
  129.  * access register virtual address. In the corresponding
  130.  * structures the member variable for the entry number is
  131.  * called "local_tlb_entry" - it contrast with the "tlb_entry"
  132.  * for the US data access register VA structure. The rationale
  133.  * behind this is to prevent careless mistakes in the code
  134.  * caused by setting only the entry number and not the TLB
  135.  * number in the US3 code (when taking the code from US).
  136.  */
  137.  
  138. union dtlb_data_access_addr {
  139.     uint64_t value;
  140.     struct {
  141.         uint64_t : 45;
  142.         unsigned : 1;
  143.         unsigned tlb_number : 2;
  144.         unsigned : 4;
  145.         unsigned local_tlb_entry : 9;
  146.         unsigned : 3;
  147.     } __attribute__ ((packed));
  148. };
  149. typedef union dtlb_data_access_addr dtlb_data_access_addr_t;
  150. typedef union dtlb_data_access_addr dtlb_tag_read_addr_t;
  151.  
  152. union itlb_data_access_addr {
  153.     uint64_t value;
  154.     struct {
  155.         uint64_t : 45;
  156.         unsigned : 1;
  157.         unsigned tlb_number : 2;
  158.         unsigned : 6;
  159.         unsigned local_tlb_entry : 7;
  160.         unsigned : 3;
  161.     } __attribute__ ((packed));
  162. };
  163. typedef union itlb_data_access_addr itlb_data_access_addr_t;
  164. typedef union itlb_data_access_addr itlb_tag_read_addr_t;
  165.  
  166. #endif
  167.  
  168. /** I-/D-TLB Tag Read Register. */
  169. union tlb_tag_read_reg {
  170.     uint64_t value;
  171.     struct {
  172.         uint64_t vpn : 51;  /**< Virtual Address bits 63:13. */
  173.         unsigned context : 13;  /**< Context identifier. */
  174.     } __attribute__ ((packed));
  175. };
  176. typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
  177. typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
  178.  
  179.  
  180. /** TLB Demap Operation Address. */
  181. union tlb_demap_addr {
  182.     uint64_t value;
  183.     struct {
  184.         uint64_t vpn: 51;   /**< Virtual Address bits 63:13. */
  185. #if defined (US)
  186.         unsigned : 6;       /**< Ignored. */
  187.         unsigned type : 1;  /**< The type of demap operation. */
  188. #elif defined (US3)
  189.         unsigned : 5;       /**< Ignored. */
  190.         unsigned type: 2;   /**< The type of demap operation. */
  191. #endif
  192.         unsigned context : 2;   /**< Context register selection. */
  193.         unsigned : 4;       /**< Zero. */
  194.     } __attribute__ ((packed));
  195. };
  196. typedef union tlb_demap_addr tlb_demap_addr_t;
  197.  
  198. /** TLB Synchronous Fault Status Register. */
  199. union tlb_sfsr_reg {
  200.     uint64_t value;
  201.     struct {
  202. #if defined (US)
  203.         unsigned long : 40; /**< Implementation dependent. */
  204.         unsigned asi : 8;   /**< ASI. */
  205.         unsigned : 2;
  206.         unsigned ft : 7;    /**< Fault type. */
  207. #elif defined (US3)
  208.         unsigned long : 39; /**< Implementation dependent. */
  209.         unsigned nf : 1;    /**< Non-faulting load. */
  210.         unsigned asi : 8;   /**< ASI. */
  211.         unsigned tm : 1;    /**< I-TLB miss. */
  212.         unsigned : 3;       /**< Reserved. */
  213.         unsigned ft : 5;    /**< Fault type. */
  214. #endif
  215.         unsigned e : 1;     /**< Side-effect bit. */
  216.         unsigned ct : 2;    /**< Context Register selection. */
  217.         unsigned pr : 1;    /**< Privilege bit. */
  218.         unsigned w : 1;     /**< Write bit. */
  219.         unsigned ow : 1;    /**< Overwrite bit. */
  220.         unsigned fv : 1;    /**< Fault Valid bit. */
  221.     } __attribute__ ((packed));
  222. };
  223. typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
  224.  
  225. #if defined (US3)
  226.  
  227. /*
  228.  * Functions for determining the number of entries in TLBs. They either return
  229.  * a constant value or a value based on the CPU autodetection.
  230.  */
  231.  
  232. /**
  233.  * Determine the number od entries in the DMMU's small TLB.
  234.  */
  235. static inline uint16_t tlb_dsmall_size(void)
  236. {
  237.     return 16;
  238. }
  239.  
  240. /**
  241.  * Determine the number od entries in each DMMU's big TLB.
  242.  */
  243. static inline uint16_t tlb_dbig_size(void)
  244. {
  245.     return 512;
  246. }
  247.  
  248. /**
  249.  * Determine the number od entries in the IMMU's small TLB.
  250.  */
  251. static inline uint16_t tlb_ismall_size(void)
  252. {
  253.     return 16;
  254. }
  255.  
  256. /**
  257.  * Determine the number od entries in the IMMU's big TLB.
  258.  */
  259. static inline uint16_t tlb_ibig_size(void)
  260. {
  261.     if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
  262.         return 512;
  263.     else
  264.         return 128;
  265. }
  266.  
  267. #endif
  268.  
  269. /** Read MMU Primary Context Register.
  270.  *
  271.  * @return Current value of Primary Context Register.
  272.  */
  273. static inline uint64_t mmu_primary_context_read(void)
  274. {
  275.     return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
  276. }
  277.  
  278. /** Write MMU Primary Context Register.
  279.  *
  280.  * @param v New value of Primary Context Register.
  281.  */
  282. static inline void mmu_primary_context_write(uint64_t v)
  283. {
  284.     asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
  285.     flush_pipeline();
  286. }
  287.  
  288. /** Read MMU Secondary Context Register.
  289.  *
  290.  * @return Current value of Secondary Context Register.
  291.  */
  292. static inline uint64_t mmu_secondary_context_read(void)
  293. {
  294.     return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
  295. }
  296.  
  297. /** Write MMU Primary Context Register.
  298.  *
  299.  * @param v New value of Primary Context Register.
  300.  */
  301. static inline void mmu_secondary_context_write(uint64_t v)
  302. {
  303.     asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
  304.     flush_pipeline();
  305. }
  306.  
  307. #if defined (US)
  308.  
  309. /** Read IMMU TLB Data Access Register.
  310.  *
  311.  * @param entry TLB Entry index.
  312.  *
  313.  * @return Current value of specified IMMU TLB Data Access Register.
  314.  */
  315. static inline uint64_t itlb_data_access_read(index_t entry)
  316. {
  317.     itlb_data_access_addr_t reg;
  318.    
  319.     reg.value = 0;
  320.     reg.tlb_entry = entry;
  321.     return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
  322. }
  323.  
  324. /** Write IMMU TLB Data Access Register.
  325.  *
  326.  * @param entry TLB Entry index.
  327.  * @param value Value to be written.
  328.  */
  329. static inline void itlb_data_access_write(index_t entry, uint64_t value)
  330. {
  331.     itlb_data_access_addr_t reg;
  332.    
  333.     reg.value = 0;
  334.     reg.tlb_entry = entry;
  335.     asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
  336.     flush_pipeline();
  337. }
  338.  
  339. /** Read DMMU TLB Data Access Register.
  340.  *
  341.  * @param entry TLB Entry index.
  342.  *
  343.  * @return Current value of specified DMMU TLB Data Access Register.
  344.  */
  345. static inline uint64_t dtlb_data_access_read(index_t entry)
  346. {
  347.     dtlb_data_access_addr_t reg;
  348.    
  349.     reg.value = 0;
  350.     reg.tlb_entry = entry;
  351.     return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
  352. }
  353.  
  354. /** Write DMMU TLB Data Access Register.
  355.  *
  356.  * @param entry TLB Entry index.
  357.  * @param value Value to be written.
  358.  */
  359. static inline void dtlb_data_access_write(index_t entry, uint64_t value)
  360. {
  361.     dtlb_data_access_addr_t reg;
  362.    
  363.     reg.value = 0;
  364.     reg.tlb_entry = entry;
  365.     asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
  366.     membar();
  367. }
  368.  
  369. /** Read IMMU TLB Tag Read Register.
  370.  *
  371.  * @param entry TLB Entry index.
  372.  *
  373.  * @return Current value of specified IMMU TLB Tag Read Register.
  374.  */
  375. static inline uint64_t itlb_tag_read_read(index_t entry)
  376. {
  377.     itlb_tag_read_addr_t tag;
  378.  
  379.     tag.value = 0;
  380.     tag.tlb_entry = entry;
  381.     return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
  382. }
  383.  
  384. /** Read DMMU TLB Tag Read Register.
  385.  *
  386.  * @param entry TLB Entry index.
  387.  *
  388.  * @return Current value of specified DMMU TLB Tag Read Register.
  389.  */
  390. static inline uint64_t dtlb_tag_read_read(index_t entry)
  391. {
  392.     dtlb_tag_read_addr_t tag;
  393.  
  394.     tag.value = 0;
  395.     tag.tlb_entry = entry;
  396.     return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
  397. }
  398.  
  399. #elif defined (US3)
  400.  
  401.  
  402. /** Read IMMU TLB Data Access Register.
  403.  *
  404.  * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
  405.  * @param entry TLB Entry index.
  406.  *
  407.  * @return Current value of specified IMMU TLB Data Access Register.
  408.  */
  409. static inline uint64_t itlb_data_access_read(int tlb, index_t entry)
  410. {
  411.     itlb_data_access_addr_t reg;
  412.    
  413.     reg.value = 0;
  414.     reg.tlb_number = tlb;
  415.     reg.local_tlb_entry = entry;
  416.     return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
  417. }
  418.  
  419. /** Write IMMU TLB Data Access Register.
  420.  * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
  421.  * @param entry TLB Entry index.
  422.  * @param value Value to be written.
  423.  */
  424. static inline void itlb_data_access_write(int tlb, index_t entry,
  425.     uint64_t value)
  426. {
  427.     itlb_data_access_addr_t reg;
  428.    
  429.     reg.value = 0;
  430.     reg.tlb_number = tlb;
  431.     reg.local_tlb_entry = entry;
  432.     asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
  433.     flush_pipeline();
  434. }
  435.  
  436. /** Read DMMU TLB Data Access Register.
  437.  *
  438.  * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
  439.  * @param entry TLB Entry index.
  440.  *
  441.  * @return Current value of specified DMMU TLB Data Access Register.
  442.  */
  443. static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
  444. {
  445.     dtlb_data_access_addr_t reg;
  446.    
  447.     reg.value = 0;
  448.     reg.tlb_number = tlb;
  449.     reg.local_tlb_entry = entry;
  450.     return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
  451. }
  452.  
  453. /** Write DMMU TLB Data Access Register.
  454.  *
  455.  * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)  
  456.  * @param entry TLB Entry index.
  457.  * @param value Value to be written.
  458.  */
  459. static inline void dtlb_data_access_write(int tlb, index_t entry,
  460.     uint64_t value)
  461. {
  462.     dtlb_data_access_addr_t reg;
  463.    
  464.     reg.value = 0;
  465.     reg.tlb_number = tlb;
  466.     reg.local_tlb_entry = entry;
  467.     asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
  468.     membar();
  469. }
  470.  
  471. /** Read IMMU TLB Tag Read Register.
  472.  *
  473.  * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
  474.  * @param entry TLB Entry index.
  475.  *
  476.  * @return Current value of specified IMMU TLB Tag Read Register.
  477.  */
  478. static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)
  479. {
  480.     itlb_tag_read_addr_t tag;
  481.  
  482.     tag.value = 0;
  483.     tag.tlb_number = tlb;
  484.     tag.local_tlb_entry = entry;
  485.     return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
  486. }
  487.  
  488. /** Read DMMU TLB Tag Read Register.
  489.  *
  490.  * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)  
  491.  * @param entry TLB Entry index.
  492.  *
  493.  * @return Current value of specified DMMU TLB Tag Read Register.
  494.  */
  495. static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry)
  496. {
  497.     dtlb_tag_read_addr_t tag;
  498.  
  499.     tag.value = 0;
  500.     tag.tlb_number = tlb;
  501.     tag.local_tlb_entry = entry;
  502.     return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
  503. }
  504.  
  505. #endif
  506.  
  507.  
  508. /** Write IMMU TLB Tag Access Register.
  509.  *
  510.  * @param v Value to be written.
  511.  */
  512. static inline void itlb_tag_access_write(uint64_t v)
  513. {
  514.     asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
  515.     flush_pipeline();
  516. }
  517.  
  518. /** Read IMMU TLB Tag Access Register.
  519.  *
  520.  * @return Current value of IMMU TLB Tag Access Register.
  521.  */
  522. static inline uint64_t itlb_tag_access_read(void)
  523. {
  524.     return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
  525. }
  526.  
  527. /** Write DMMU TLB Tag Access Register.
  528.  *
  529.  * @param v Value to be written.
  530.  */
  531. static inline void dtlb_tag_access_write(uint64_t v)
  532. {
  533.     asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
  534.     membar();
  535. }
  536.  
  537. /** Read DMMU TLB Tag Access Register.
  538.  *
  539.  * @return Current value of DMMU TLB Tag Access Register.
  540.  */
  541. static inline uint64_t dtlb_tag_access_read(void)
  542. {
  543.     return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
  544. }
  545.  
  546.  
  547. /** Write IMMU TLB Data in Register.
  548.  *
  549.  * @param v Value to be written.
  550.  */
  551. static inline void itlb_data_in_write(uint64_t v)
  552. {
  553.     asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
  554.     flush_pipeline();
  555. }
  556.  
  557. /** Write DMMU TLB Data in Register.
  558.  *
  559.  * @param v Value to be written.
  560.  */
  561. static inline void dtlb_data_in_write(uint64_t v)
  562. {
  563.     asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
  564.     membar();
  565. }
  566.  
  567. /** Read ITLB Synchronous Fault Status Register.
  568.  *
  569.  * @return Current content of I-SFSR register.
  570.  */
  571. static inline uint64_t itlb_sfsr_read(void)
  572. {
  573.     return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
  574. }
  575.  
  576. /** Write ITLB Synchronous Fault Status Register.
  577.  *
  578.  * @param v New value of I-SFSR register.
  579.  */
  580. static inline void itlb_sfsr_write(uint64_t v)
  581. {
  582.     asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
  583.     flush_pipeline();
  584. }
  585.  
  586. /** Read DTLB Synchronous Fault Status Register.
  587.  *
  588.  * @return Current content of D-SFSR register.
  589.  */
  590. static inline uint64_t dtlb_sfsr_read(void)
  591. {
  592.     return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
  593. }
  594.  
  595. /** Write DTLB Synchronous Fault Status Register.
  596.  *
  597.  * @param v New value of D-SFSR register.
  598.  */
  599. static inline void dtlb_sfsr_write(uint64_t v)
  600. {
  601.     asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
  602.     membar();
  603. }
  604.  
  605. /** Read DTLB Synchronous Fault Address Register.
  606.  *
  607.  * @return Current content of D-SFAR register.
  608.  */
  609. static inline uint64_t dtlb_sfar_read(void)
  610. {
  611.     return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
  612. }
  613.  
  614. /** Perform IMMU TLB Demap Operation.
  615.  *
  616.  * @param type
  617.  *  Selects between context and page demap
  618.  *  (and entire MMU demap on US3).
  619.  * @param context_encoding Specifies which Context register has Context ID for
  620.  *  demap.
  621.  * @param page Address which is on the page to be demapped.
  622.  */
  623. static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
  624. {
  625.     tlb_demap_addr_t da;
  626.     page_address_t pg;
  627.    
  628.     da.value = 0;
  629.     pg.address = page;
  630.    
  631.     da.type = type;
  632.     da.context = context_encoding;
  633.     da.vpn = pg.vpn;
  634.    
  635.     asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the
  636.                              * address within the
  637.                              * ASI */
  638.     flush_pipeline();
  639. }
  640.  
  641. /** Perform DMMU TLB Demap Operation.
  642.  *
  643.  * @param type
  644.  *  Selects between context and page demap
  645.  *  (and entire MMU demap on US3).
  646.  * @param context_encoding Specifies which Context register has Context ID for
  647.  *   demap.
  648.  * @param page Address which is on the page to be demapped.
  649.  */
  650. static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
  651. {
  652.     tlb_demap_addr_t da;
  653.     page_address_t pg;
  654.    
  655.     da.value = 0;
  656.     pg.address = page;
  657.    
  658.     da.type = type;
  659.     da.context = context_encoding;
  660.     da.vpn = pg.vpn;
  661.    
  662.     asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the
  663.                              * address within the
  664.                              * ASI */
  665.     membar();
  666. }
  667.  
  668. extern void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate);
  669. extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate);
  670. extern void fast_data_access_protection(tlb_tag_access_reg_t tag , istate_t *istate);
  671.  
  672. extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable);
  673.  
  674. extern void dump_sfsr_and_sfar(void);
  675.  
  676. #endif /* !def __ASM__ */
  677.  
  678. #endif
  679.  
  680. /** @}
  681.  */
  682.