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  1. /*
  2.  * Copyright (c) 2005 - 2006 Jakub Jermar
  3.  * Copyright (c) 2006 Jakub Vana
  4.  * All rights reserved.
  5.  *
  6.  * Redistribution and use in source and binary forms, with or without
  7.  * modification, are permitted provided that the following conditions
  8.  * are met:
  9.  *
  10.  * - Redistributions of source code must retain the above copyright
  11.  *   notice, this list of conditions and the following disclaimer.
  12.  * - Redistributions in binary form must reproduce the above copyright
  13.  *   notice, this list of conditions and the following disclaimer in the
  14.  *   documentation and/or other materials provided with the distribution.
  15.  * - The name of the author may not be used to endorse or promote products
  16.  *   derived from this software without specific prior written permission.
  17.  *
  18.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28.  */
  29.  
  30. /** @addtogroup ia64mm 
  31.  * @{
  32.  */
  33. /** @file
  34.  */
  35.  
  36. #ifndef KERN_ia64_PAGE_H_
  37. #define KERN_ia64_PAGE_H_
  38.  
  39. #include <arch/mm/frame.h>
  40.  
  41. #define PAGE_SIZE   FRAME_SIZE
  42. #define PAGE_WIDTH  FRAME_WIDTH
  43.  
  44. #ifdef KERNEL
  45.  
  46. /** Bit width of the TLB-locked portion of kernel address space. */
  47. #define KERNEL_PAGE_WIDTH       28  /* 256M */
  48. #define IO_PAGE_WIDTH           26  /* 64M */
  49. #define FW_PAGE_WIDTH           28  /* 256M */
  50.  
  51. #define USPACE_IO_PAGE_WIDTH        12  /* 4K */
  52.  
  53.  
  54.  
  55. /** Staticly mapped IO spaces - offsets to 0xe...00 of virtual adresses
  56. becauce of "minimal virtual bits implemented is 51"
  57. it is possible to have here values up to 0x0007000000000000
  58. */
  59.  
  60. /* Firmware area (bellow 4GB in phys mem) */
  61. #define FW_OFFSET             0x00000000F0000000
  62. /* Legacy IO space */
  63. #define IO_OFFSET             0x0001000000000000
  64. /* Videoram - now mapped to 0 as VGA text mode vram on 0xb8000*/
  65. #define VIO_OFFSET            0x0002000000000000
  66.  
  67.  
  68.  
  69.  
  70. #define PPN_SHIFT           12
  71.  
  72. #define VRN_SHIFT           61
  73. #define VRN_MASK            (7LL << VRN_SHIFT)
  74. #define VA2VRN(va)          ((va)>>VRN_SHIFT)
  75.  
  76. #ifdef __ASM__
  77. #define VRN_KERNEL          7
  78. #else
  79. #define VRN_KERNEL          7LL
  80. #endif
  81.  
  82. #define REGION_REGISTERS        8
  83.  
  84. #define KA2PA(x)    ((uintptr_t) (x-(VRN_KERNEL<<VRN_SHIFT)))
  85. #define PA2KA(x)    ((uintptr_t) (x+(VRN_KERNEL<<VRN_SHIFT)))
  86.  
  87. #define VHPT_WIDTH          20  /* 1M */
  88. #define VHPT_SIZE           (1 << VHPT_WIDTH)
  89.  
  90. #define PTA_BASE_SHIFT          15
  91.  
  92. /** Memory Attributes. */
  93. #define MA_WRITEBACK    0x0
  94. #define MA_UNCACHEABLE  0x4
  95.  
  96. /** Privilege Levels. Only the most and the least privileged ones are ever used. */
  97. #define PL_KERNEL   0x0
  98. #define PL_USER     0x3
  99.  
  100. /* Access Rigths. Only certain combinations are used by the kernel. */
  101. #define AR_READ     0x0
  102. #define AR_EXECUTE  0x1
  103. #define AR_WRITE    0x2
  104.  
  105. #ifndef __ASM__
  106.  
  107. #include <arch/mm/as.h>
  108. #include <arch/mm/frame.h>
  109. #include <arch/interrupt.h>
  110. #include <arch/barrier.h>
  111. #include <arch/mm/asid.h>
  112. #include <arch/types.h>
  113. #include <debug.h>
  114.  
  115. struct vhpt_tag_info {
  116.     unsigned long long tag : 63;
  117.     unsigned ti : 1;
  118. } __attribute__ ((packed));
  119.  
  120. union vhpt_tag {
  121.     struct vhpt_tag_info tag_info;
  122.     unsigned tag_word;
  123. };
  124.  
  125. struct vhpt_entry_present {
  126.     /* Word 0 */
  127.     unsigned p : 1;
  128.     unsigned : 1;
  129.     unsigned ma : 3;
  130.     unsigned a : 1;
  131.     unsigned d : 1;
  132.     unsigned pl : 2;
  133.     unsigned ar : 3;
  134.     unsigned long long ppn : 38;
  135.     unsigned : 2;
  136.     unsigned ed : 1;
  137.     unsigned ig1 : 11;
  138.    
  139.     /* Word 1 */
  140.     unsigned : 2;
  141.     unsigned ps : 6;
  142.     unsigned key : 24;
  143.     unsigned : 32;
  144.    
  145.     /* Word 2 */
  146.     union vhpt_tag tag;
  147.    
  148.     /* Word 3 */                                                   
  149.     uint64_t ig3 : 64;
  150. } __attribute__ ((packed));
  151.  
  152. struct vhpt_entry_not_present {
  153.     /* Word 0 */
  154.     unsigned p : 1;
  155.     unsigned long long ig0 : 52;
  156.     unsigned ig1 : 11;
  157.    
  158.     /* Word 1 */
  159.     unsigned : 2;
  160.     unsigned ps : 6;
  161.     unsigned long long ig2 : 56;
  162.  
  163.     /* Word 2 */
  164.     union vhpt_tag tag;
  165.    
  166.     /* Word 3 */                                                   
  167.     uint64_t ig3 : 64;
  168. } __attribute__ ((packed));
  169.  
  170. typedef union vhpt_entry {
  171.     struct vhpt_entry_present present;
  172.     struct vhpt_entry_not_present not_present;
  173.     uint64_t word[4];
  174. } vhpt_entry_t;
  175.  
  176. struct region_register_map {
  177.     unsigned ve : 1;
  178.     unsigned : 1;
  179.     unsigned ps : 6;
  180.     unsigned rid : 24;
  181.     unsigned : 32;
  182. } __attribute__ ((packed));
  183.  
  184. typedef union region_register {
  185.     struct region_register_map map;
  186.     unsigned long long word;
  187. } region_register;
  188.  
  189. struct pta_register_map {
  190.     unsigned ve : 1;
  191.     unsigned : 1;
  192.     unsigned size : 6;
  193.     unsigned vf : 1;
  194.     unsigned : 6;
  195.     unsigned long long base : 49;
  196. } __attribute__ ((packed));
  197.  
  198. typedef union pta_register {
  199.     struct pta_register_map map;
  200.     uint64_t word;
  201. } pta_register;
  202.  
  203. /** Return Translation Hashed Entry Address.
  204.  *
  205.  * VRN bits are used to read RID (ASID) from one
  206.  * of the eight region registers registers.
  207.  *
  208.  * @param va Virtual address including VRN bits.
  209.  *
  210.  * @return Address of the head of VHPT collision chain.
  211.  */
  212. static inline uint64_t thash(uint64_t va)
  213. {
  214.     uint64_t ret;
  215.  
  216.     asm volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));
  217.  
  218.     return ret;
  219. }
  220.  
  221. /** Return Translation Hashed Entry Tag.
  222.  *
  223.  * VRN bits are used to read RID (ASID) from one
  224.  * of the eight region registers.
  225.  *
  226.  * @param va Virtual address including VRN bits.
  227.  *
  228.  * @return The unique tag for VPN and RID in the collision chain returned by thash().
  229.  */
  230. static inline uint64_t ttag(uint64_t va)
  231. {
  232.     uint64_t ret;
  233.  
  234.     asm volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));
  235.  
  236.     return ret;
  237. }
  238.  
  239. /** Read Region Register.
  240.  *
  241.  * @param i Region register index.
  242.  *
  243.  * @return Current contents of rr[i].
  244.  */
  245. static inline uint64_t rr_read(index_t i)
  246. {
  247.     uint64_t ret;
  248.     ASSERT(i < REGION_REGISTERS);
  249.     asm volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT));
  250.     return ret;
  251. }
  252.  
  253. /** Write Region Register.
  254.  *
  255.  * @param i Region register index.
  256.  * @param v Value to be written to rr[i].
  257.  */
  258. static inline void rr_write(index_t i, uint64_t v)
  259. {
  260.     ASSERT(i < REGION_REGISTERS);
  261.     asm volatile (
  262.         "mov rr[%0] = %1\n"
  263.         :
  264.         : "r" (i << VRN_SHIFT), "r" (v)
  265.     );
  266. }
  267.  
  268. /** Read Page Table Register.
  269.  *
  270.  * @return Current value stored in PTA.
  271.  */
  272. static inline uint64_t pta_read(void)
  273. {
  274.     uint64_t ret;
  275.    
  276.     asm volatile ("mov %0 = cr.pta\n" : "=r" (ret));
  277.    
  278.     return ret;
  279. }
  280.  
  281. /** Write Page Table Register.
  282.  *
  283.  * @param v New value to be stored in PTA.
  284.  */
  285. static inline void pta_write(uint64_t v)
  286. {
  287.     asm volatile ("mov cr.pta = %0\n" : : "r" (v));
  288. }
  289.  
  290. extern void page_arch_init(void);
  291.  
  292. extern vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid);
  293. extern bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v);
  294. extern void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags);
  295.  
  296. #endif /* __ASM__ */
  297.  
  298. #endif /* KERNEL */
  299.  
  300. #endif
  301.  
  302. /** @}
  303.  */
  304.