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  1. /*
  2.  * Copyright (c) 2006 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup sparc64mm
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #include <arch/mm/as.h>
  36. #include <arch/mm/tlb.h>
  37. #include <genarch/mm/page_ht.h>
  38. #include <genarch/mm/asid_fifo.h>
  39. #include <debug.h>
  40. #include <config.h>
  41.  
  42. #ifdef CONFIG_TSB
  43. #include <arch/mm/tsb.h>
  44. #include <arch/memstr.h>
  45. #include <arch/asm.h>
  46. #include <mm/frame.h>
  47. #include <bitops.h>
  48. #include <macros.h>
  49. #endif /* CONFIG_TSB */
  50.  
  51. /** Architecture dependent address space init. */
  52. void as_arch_init(void)
  53. {
  54.     if (config.cpu_active == 1) {
  55.         as_operations = &as_ht_operations;
  56.         asid_fifo_init();
  57.     }
  58. }
  59.  
  60. int as_constructor_arch(as_t *as, int flags)
  61. {
  62. #ifdef CONFIG_TSB
  63.     /*
  64.      * The order must be calculated with respect to the emulated
  65.      * 16K page size.
  66.      */
  67.     int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
  68.         sizeof(tsb_entry_t)) >> FRAME_WIDTH);
  69.  
  70.     uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA);
  71.  
  72.     if (!tsb)
  73.         return -1;
  74.  
  75.     as->arch.itsb = (tsb_entry_t *) tsb;
  76.     as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT *
  77.         sizeof(tsb_entry_t));
  78.  
  79.     memsetb(as->arch.itsb,
  80.         (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0);
  81. #endif
  82.     return 0;
  83. }
  84.  
  85. int as_destructor_arch(as_t *as)
  86. {
  87. #ifdef CONFIG_TSB
  88.     /*
  89.      * The count must be calculated with respect to the emualted 16K page
  90.      * size.
  91.      */
  92.     size_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
  93.         sizeof(tsb_entry_t)) >> FRAME_WIDTH;
  94.     frame_free(KA2PA((uintptr_t) as->arch.itsb));
  95.     return cnt;
  96. #else
  97.     return 0;
  98. #endif
  99. }
  100.  
  101. int as_create_arch(as_t *as, int flags)
  102. {
  103. #ifdef CONFIG_TSB
  104.     tsb_invalidate(as, 0, (size_t) -1);
  105. #endif
  106.     return 0;
  107. }
  108.  
  109. /** Perform sparc64-specific tasks when an address space becomes active on the
  110.  * processor.
  111.  *
  112.  * Install ASID and map TSBs.
  113.  *
  114.  * @param as Address space.
  115.  */
  116. void as_install_arch(as_t *as)
  117. {
  118.     tlb_context_reg_t ctx;
  119.    
  120.     /*
  121.      * Note that we don't and may not lock the address space. That's ok
  122.      * since we only read members that are currently read-only.
  123.      *
  124.      * Moreover, the as->asid is protected by asidlock, which is being held.
  125.      */
  126.    
  127.     /*
  128.      * Write ASID to secondary context register. The primary context
  129.      * register has to be set from TL>0 so it will be filled from the
  130.      * secondary context register from the TL=1 code just before switch to
  131.      * userspace.
  132.      */
  133.     ctx.v = 0;
  134.     ctx.context = as->asid;
  135.     mmu_secondary_context_write(ctx.v);
  136.  
  137. #ifdef CONFIG_TSB  
  138.     uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
  139.  
  140.     ASSERT(as->arch.itsb && as->arch.dtsb);
  141.  
  142.     uintptr_t tsb = (uintptr_t) as->arch.itsb;
  143.        
  144.     if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
  145.         /*
  146.          * TSBs were allocated from memory not covered
  147.          * by the locked 4M kernel DTLB entry. We need
  148.          * to map both TSBs explicitly.
  149.          */
  150.         dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
  151.         dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true);
  152.     }
  153.        
  154.     /*
  155.      * Setup TSB Base registers.
  156.      */
  157.     tsb_base_reg_t tsb_base;
  158.        
  159.     tsb_base.value = 0;
  160.     tsb_base.size = TSB_SIZE;
  161.     tsb_base.split = 0;
  162.  
  163.     tsb_base.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH;
  164.     itsb_base_write(tsb_base.value);
  165.     tsb_base.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH;
  166.     dtsb_base_write(tsb_base.value);
  167.    
  168. #if defined (US3)
  169.     /*
  170.      * Clear the extension registers.
  171.      * In HelenOS, primary and secondary context registers contain
  172.      * equal values and kernel misses (context 0, ie. the nucleus context)
  173.      * are excluded from the TSB miss handler, so it makes no sense
  174.      * to have separate TSBs for primary, secondary and nucleus contexts.
  175.      * Clearing the extension registers will ensure that the value of the
  176.      * TSB Base register will be used as an address of TSB, making the code
  177.      * compatible with the US port.
  178.      */
  179.     itsb_primary_extension_write(0);
  180.     itsb_nucleus_extension_write(0);
  181.     dtsb_primary_extension_write(0);
  182.     dtsb_secondary_extension_write(0);
  183.     dtsb_nucleus_extension_write(0);
  184. #endif
  185. #endif
  186. }
  187.  
  188. /** Perform sparc64-specific tasks when an address space is removed from the
  189.  * processor.
  190.  *
  191.  * Demap TSBs.
  192.  *
  193.  * @param as Address space.
  194.  */
  195. void as_deinstall_arch(as_t *as)
  196. {
  197.  
  198.     /*
  199.      * Note that we don't and may not lock the address space. That's ok
  200.      * since we only read members that are currently read-only.
  201.      *
  202.      * Moreover, the as->asid is protected by asidlock, which is being held.
  203.      */
  204.  
  205. #ifdef CONFIG_TSB
  206.     uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
  207.  
  208.     ASSERT(as->arch.itsb && as->arch.dtsb);
  209.  
  210.     uintptr_t tsb = (uintptr_t) as->arch.itsb;
  211.        
  212.     if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
  213.         /*
  214.          * TSBs were allocated from memory not covered
  215.          * by the locked 4M kernel DTLB entry. We need
  216.          * to demap the entry installed by as_install_arch().
  217.          */
  218.         dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
  219.     }
  220. #endif
  221. }
  222.  
  223. /** @}
  224.  */
  225.