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  1. #include <unistd.h>
  2. #include <ddi.h>
  3. #include <libarch/ddi.h>
  4. #include <stdio.h>
  5.  
  6. #include "internal.h"
  7.  
  8. /* physical addresses and offsets */
  9. //#define U2P_BASE        0x1FE00000000
  10. #define U2P_BASE        0x1ca00000000
  11. #define PCI_CONF_OFFSET   0x001000000
  12. #define PCI_CONF_SIZE     0x001000000
  13. #define PCI_CONF_BASE  (U2P_BASE + PCI_CONF_OFFSET)
  14.  
  15. /* virtual address of PCI configuration space */
  16. static void *conf_addr = 0;  
  17.  
  18. /*
  19.  * virtual address of specified PCI configuration register:
  20.  * bus ... bus number (0 for top level PCI bus B, 1 for top level PCI bus A)
  21.  * dev ... device number (0 - 15)
  22.  * fn  ... function number (0 - 7)
  23.  * reg ... register number (register's position within PCI configuration header)
  24.  **/
  25. #define CONF_ADDR(bus, dev, fn, reg)   ((void *)(conf_addr + ((bus << 16) | (dev << 11) | (fn << 8) | (reg << 0))))
  26.  
  27.  
  28.  
  29. static void us2i_init(struct pci_access *a)
  30. {  
  31. }
  32.  
  33. static void us2i_cleanup(struct pci_access *a UNUSED)
  34. {
  35. }
  36.  
  37. static inline uint64_t pio_read_64(uint64_t *port)
  38. {
  39.     uint64_t rv;
  40.  
  41.     rv = *port;
  42.     memory_barrier();
  43.  
  44.     return rv;
  45. }
  46.  
  47.  
  48. // read whole 8-byte blocks
  49. static void us2i_read_aligned(int bus, int dev, int fn, int pos, byte * buf, int len)
  50. {
  51.     uint64_t aux;
  52.    
  53.     int offset = pos % 8;
  54.     int aligned_pos = pos - offset;
  55.    
  56.     if (len + offset > 8) {
  57.         len = 8 - offset;
  58.     }
  59.    
  60.     void *addr = CONF_ADDR(bus, dev, fn, aligned_pos);
  61.     aux = pio_read_64(addr);
  62.    
  63.     int i;
  64.     for (i = 0; i < len; i++) {
  65.         buf[i] = ((byte *)(&aux))[offset + i];
  66.     }  
  67. }
  68.  
  69. static int us2i_detect(struct pci_access *a)
  70. {  
  71.     /*
  72.      * Gain control over PCI configuration ports.
  73.      */
  74.     if (pio_enable((void *)PCI_CONF_BASE, PCI_CONF_SIZE, &conf_addr)) {
  75.         return 0;
  76.     }  
  77.    
  78.     u16 vendor_id, device_id;
  79.     us2i_read_aligned(0, 0, 0, PCI_VENDOR_ID, &vendor_id, 2);
  80.     vendor_id = cpu_to_le16(vendor_id);
  81.     us2i_read_aligned(0, 0, 0, PCI_DEVICE_ID, &device_id, 2);
  82.     device_id = cpu_to_le16(device_id);
  83.  
  84.     //int vendor_id = le16_to_cpu(pio_read_16(CONF_ADDR(0, 0, 0, PCI_VENDOR_ID))); 
  85.     //int device_id = le16_to_cpu(pio_read_16(CONF_ADDR(0, 0, 0, PCI_DEVICE_ID)));
  86.     //int vendor_id = pio_read_8(CONF_ADDR(0, 0, 0, PCI_VENDOR_ID));
  87.     //vendor_id = vendor_id + pio_read_8(CONF_ADDR(0, 0, 0, PCI_VENDOR_ID + 1)) << 8;
  88.     //int device_id = pio_read_8(CONF_ADDR(0, 0, 0, PCI_DEVICE_ID));
  89.     //device_id = device_id | pio_read_8(CONF_ADDR(0, 0, 0, PCI_DEVICE_ID + 1)) << 8;
  90.    
  91.     printf("PCI: vendor id = %x\n", vendor_id);
  92.     printf("PCI: device id = %x\n", device_id);
  93.  
  94.     // return vendor_id == 0x108E && device_id == 0x8000; // should be Psycho from Sun Microsystems ???
  95.     //return vendor_id == 0x108E /*&& device_id == 0x1000*/; // should be Psycho from Sun Microsystems
  96.     return 1;
  97. }
  98.  
  99. static int us2i_read(struct pci_dev *d, int pos, byte * buf, int len)
  100. {
  101.     void * addr = CONF_ADDR(d->bus, d->dev, d->func, pos); 
  102.    
  103.     if (pos >= 256)
  104.         return 0;      
  105.  
  106.     switch (len) {
  107.     case 1:
  108.         us2i_read_aligned(d->bus, d->dev, d->func, pos, buf, len);
  109.         break;
  110.     case 2:
  111.         us2i_read_aligned(d->bus, d->dev, d->func, pos, buf, len);
  112.         ((u16 *) buf)[0] = cpu_to_le16(*((u16 *) buf));
  113.         break;
  114.     case 4:
  115.         us2i_read_aligned(d->bus, d->dev, d->func, pos, buf, len);
  116.         ((u32 *) buf)[0] = cpu_to_le32(*((u32 *) buf));    
  117.         break;
  118.     default:
  119.         return pci_generic_block_read(d, pos, buf, len);
  120.     }
  121.     return 1;
  122.    
  123.     /*
  124.     void * addr = CONF_ADDR(d->bus, d->dev, d->func, pos); 
  125.    
  126.     if (pos >= 256)
  127.         return 0;      
  128.  
  129.     switch (len) {
  130.     case 1:
  131.         buf[0] = pio_read_8(addr);
  132.         break;
  133.     case 2:
  134.         ((u16 *) buf)[0] = cpu_to_le16(pio_read_16(addr));
  135.         break;
  136.     case 4:
  137.         ((u32 *) buf)[0] = cpu_to_le32(pio_read_32(addr));     
  138.         break;
  139.     default:
  140.         return pci_generic_block_read(d, pos, buf, len);
  141.     }
  142.     return 1; */
  143.    
  144.     /*if (pos >= 256)
  145.         return 0;      
  146.  
  147.     switch (len) {
  148.     case 1:
  149.         buf[0] = pio_read_8(CONF_ADDR(d->bus, d->dev, d->func, pos));
  150.         break;
  151.     case 2:
  152.         us2i_read(d, pos + 1, buf, 1);   // unlike PCI, sparc uses big endian
  153.         us2i_read(d, pos, buf + 1, 1);
  154.         break;
  155.     case 4:
  156.         us2i_read(d, pos + 3, buf, 1);  // endians in an ugly way ... FIX ME
  157.         us2i_read(d, pos + 2, buf + 1, 1);
  158.         us2i_read(d, pos + 1, buf + 2, 1);
  159.         us2i_read(d, pos, buf + 3, 1);     
  160.         break;
  161.     default:
  162.         return pci_generic_block_read(d, pos, buf, len);
  163.     }
  164.     return 1;*/
  165. }
  166.  
  167. static int us2i_write(struct pci_dev *d, int pos, byte * buf, int len)
  168. {
  169.     void * addr = CONF_ADDR(d->bus, d->dev, d->func, pos);
  170.  
  171.     if (pos >= 256)
  172.         return 0;
  173.  
  174.     switch (len) {
  175.     case 1:
  176.         pio_write_8(CONF_ADDR(d->bus, d->dev, d->func, pos), buf[0]);
  177.         break;
  178.     case 2:
  179.         pio_write_16(addr, le16_to_cpu(((u16 *) buf)[0]));
  180.         break;
  181.     case 4:
  182.         pio_write_32(addr, le32_to_cpu(((u32 *) buf)[0]));
  183.         break;
  184.     default:
  185.         return pci_generic_block_write(d, pos, buf, len);
  186.     }
  187.     return 1;
  188. }
  189.  
  190.  
  191. struct pci_methods pm_us2i = {
  192.     "Ultra Sparc IIi",
  193.     NULL,           /* config */
  194.     us2i_detect,
  195.     us2i_init,
  196.     us2i_cleanup,
  197.     pci_generic_scan,
  198.     pci_generic_fill_info,
  199.     us2i_read,
  200.     us2i_write,
  201.     NULL,           /* init_dev */
  202.     NULL            /* cleanup_dev */
  203. };