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  1. /*
  2.  * Copyright (c) 2007 Petr Stepan
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup arm32
  30.  * @{
  31.  */
  32. /** @file
  33.  *  @brief Exception handlers and exception initialization routines.
  34.  */
  35.  
  36. #include <arch/exception.h>
  37. #include <arch/debug/print.h>
  38. #include <arch/memstr.h>
  39. #include <arch/regutils.h>
  40. #include <interrupt.h>
  41. #include <arch/machine.h>
  42. #include <arch/mm/page_fault.h>
  43. #include <arch/barrier.h>
  44. #include <print.h>
  45. #include <syscall/syscall.h>
  46.  
  47. /** Offset used in calculation of exception handler's relative address.
  48.  *
  49.  * @see install_handler()
  50.  */
  51. #define PREFETCH_OFFSET      0x8
  52.  
  53. /** LDR instruction's code */
  54. #define LDR_OPCODE           0xe59ff000
  55.  
  56. /** Number of exception vectors. */
  57. #define EXC_VECTORS          8
  58.  
  59. /** Size of memory block occupied by exception vectors. */
  60. #define EXC_VECTORS_SIZE     (EXC_VECTORS * 4)
  61.  
  62. /** Switches to kernel stack and saves all registers there.
  63.  *
  64.  * Temporary exception stack is used to save a few registers
  65.  * before stack switch takes place.
  66.  *
  67.  */
  68. inline static void setup_stack_and_save_regs()
  69. {
  70.     asm volatile (
  71.         "ldr r13, =exc_stack\n"
  72.         "stmfd r13!, {r0}\n"
  73.         "mrs r0, spsr\n"
  74.         "and r0, r0, #0x1f\n"
  75.         "cmp r0, #0x10\n"
  76.         "bne 1f\n"
  77.        
  78.         /* prev mode was usermode */
  79.         "ldmfd r13!, {r0}\n"
  80.         "ldr r13, =supervisor_sp\n"
  81.         "ldr r13, [r13]\n"
  82.         "stmfd r13!, {lr}\n"
  83.         "stmfd r13!, {r0-r12}\n"
  84.         "stmfd r13!, {r13, lr}^\n"
  85.         "mrs r0, spsr\n"
  86.         "stmfd r13!, {r0}\n"
  87.         "b 2f\n"
  88.        
  89.         /* mode was not usermode */
  90.         "1:\n"
  91.             "stmfd r13!, {r1, r2, r3}\n"
  92.             "mrs r1, cpsr\n"
  93.             "mov r2, lr\n"
  94.             "bic r1, r1, #0x1f\n"
  95.             "orr r1, r1, r0\n"
  96.             "mrs r0, cpsr\n"
  97.             "msr cpsr_c, r1\n"
  98.            
  99.             "mov r3, r13\n"
  100.             "stmfd r13!, {r2}\n"
  101.             "mov r2, lr\n"
  102.             "stmfd r13!, {r4-r12}\n"
  103.             "mov r1, r13\n"
  104.            
  105.             /* the following two lines are for debugging */
  106.             "mov sp, #0\n"
  107.             "mov lr, #0\n"
  108.             "msr cpsr_c, r0\n"
  109.            
  110.             "ldmfd r13!, {r4, r5, r6, r7}\n"
  111.             "stmfd r1!, {r4, r5, r6}\n"
  112.             "stmfd r1!, {r7}\n"
  113.             "stmfd r1!, {r2}\n"
  114.             "stmfd r1!, {r3}\n"
  115.             "mrs r0, spsr\n"
  116.             "stmfd r1!, {r0}\n"
  117.             "mov r13, r1\n"
  118.            
  119.         "2:\n"
  120.     );
  121. }
  122.  
  123. /** Returns from exception mode.
  124.  *
  125.  * Previously saved state of registers (including control register)
  126.  * is restored from the stack.
  127.  */
  128. inline static void load_regs()
  129. {
  130.     asm volatile(
  131.         "ldmfd r13!, {r0}       \n"
  132.         "msr spsr, r0           \n"
  133.         "and r0, r0, #0x1f      \n"
  134.         "cmp r0, #0x10          \n"
  135.         "bne 1f             \n"
  136.  
  137.         /* return to user mode */
  138.         "ldmfd r13!, {r13, lr}^     \n"
  139.         "b 2f               \n"
  140.  
  141.         /* return to non-user mode */
  142.     "1:\n"
  143.         "ldmfd r13!, {r1, r2}       \n"
  144.         "mrs r3, cpsr           \n"
  145.         "bic r3, r3, #0x1f      \n"
  146.         "orr r3, r3, r0         \n"
  147.         "mrs r0, cpsr           \n"
  148.         "msr cpsr_c, r3         \n"
  149.  
  150.         "mov r13, r1            \n"
  151.         "mov lr, r2         \n"
  152.         "msr cpsr_c, r0         \n"
  153.  
  154.         /* actual return */
  155.     "2:\n"
  156.         "ldmfd r13, {r0-r12, pc}^\n"
  157.     );
  158. }
  159.  
  160.  
  161. /** Switch CPU to mode in which interrupts are serviced (currently it
  162.  * is Undefined mode).
  163.  *
  164.  * The default mode for interrupt servicing (Interrupt Mode)
  165.  * can not be used because of nested interrupts (which can occur
  166.  * because interrupts are enabled in higher levels of interrupt handler).
  167.  */
  168. inline static void switch_to_irq_servicing_mode()
  169. {
  170.     /* switch to Undefined mode */
  171.     asm volatile(
  172.         /* save regs used during switching */
  173.         "stmfd sp!, {r0-r3}     \n"
  174.  
  175.         /* save stack pointer and link register to r1, r2 */
  176.         "mov r1, sp         \n"
  177.         "mov r2, lr         \n"
  178.  
  179.         /* mode switch */
  180.         "mrs r0, cpsr           \n"
  181.         "bic r0, r0, #0x1f      \n"
  182.         "orr r0, r0, #0x1b      \n"
  183.         "msr cpsr_c, r0         \n"
  184.  
  185.         /* restore saved sp and lr */
  186.         "mov sp, r1         \n"
  187.         "mov lr, r2         \n"
  188.  
  189.         /* restore original regs */
  190.         "ldmfd sp!, {r0-r3}     \n"
  191.     );
  192. }
  193.  
  194. /** Calls exception dispatch routine. */
  195. #define CALL_EXC_DISPATCH(exception) \
  196.     asm volatile ( \
  197.         "mov r0, %[exc]\n" \
  198.         "mov r1, r13\n" \
  199.         "bl exc_dispatch\n" \
  200.         :: [exc] "i" (exception) \
  201.     );\
  202.  
  203. /** General exception handler.
  204.  *
  205.  *  Stores registers, dispatches the exception,
  206.  *  and finally restores registers and returns from exception processing.
  207.  *
  208.  *  @param exception Exception number.
  209.  */
  210. #define PROCESS_EXCEPTION(exception) \
  211.     setup_stack_and_save_regs(); \
  212.     CALL_EXC_DISPATCH(exception) \
  213.     load_regs();
  214.  
  215. /** Updates specified exception vector to jump to given handler.
  216.  *
  217.  *  Addresses of handlers are stored in memory following exception vectors.
  218.  */
  219. static void install_handler(unsigned handler_addr, unsigned *vector)
  220. {
  221.     /* relative address (related to exc. vector) of the word
  222.      * where handler's address is stored
  223.     */
  224.     volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -
  225.         PREFETCH_OFFSET;
  226.    
  227.     /* make it LDR instruction and store at exception vector */
  228.     *vector = handler_address_ptr | LDR_OPCODE;
  229.     smc_coherence(*vector);
  230.    
  231.     /* store handler's address */
  232.     *(vector + EXC_VECTORS) = handler_addr;
  233.  
  234. }
  235.  
  236. /** Low-level Reset Exception handler. */
  237. static void reset_exception_entry(void)
  238. {
  239.     PROCESS_EXCEPTION(EXC_RESET);
  240. }
  241.  
  242. /** Low-level Software Interrupt Exception handler. */
  243. static void swi_exception_entry(void)
  244. {
  245.     PROCESS_EXCEPTION(EXC_SWI);
  246. }
  247.  
  248. /** Low-level Undefined Instruction Exception handler. */
  249. static void undef_instr_exception_entry(void)
  250. {
  251.     PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
  252. }
  253.  
  254. /** Low-level Fast Interrupt Exception handler. */
  255. static void fiq_exception_entry(void)
  256. {
  257.     PROCESS_EXCEPTION(EXC_FIQ);
  258. }
  259.  
  260. /** Low-level Prefetch Abort Exception handler. */
  261. static void prefetch_abort_exception_entry(void)
  262. {
  263.     asm("sub lr, lr, #4");
  264.     PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
  265. }
  266.  
  267. /** Low-level Data Abort Exception handler. */
  268. static void data_abort_exception_entry(void)
  269. {
  270.     asm("sub lr, lr, #8");
  271.     PROCESS_EXCEPTION(EXC_DATA_ABORT);
  272. }
  273.  
  274. /** Low-level Interrupt Exception handler.
  275.  *
  276.  * CPU is switched to Undefined mode before further interrupt processing
  277.  * because of possible occurence of nested interrupt exception, which
  278.  * would overwrite (and thus spoil) stack pointer.
  279.  */
  280. static void irq_exception_entry(void)
  281. {
  282.     asm("sub lr, lr, #4");
  283.     setup_stack_and_save_regs();
  284.    
  285.     switch_to_irq_servicing_mode();
  286.    
  287.     CALL_EXC_DISPATCH(EXC_IRQ)
  288.  
  289.     load_regs();
  290. }
  291.  
  292. /** Software Interrupt handler.
  293.  *
  294.  * Dispatches the syscall.
  295.  */
  296. static void swi_exception(int exc_no, istate_t *istate)
  297. {
  298.     istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2,
  299.         istate->r3, istate->r4, istate->r5, istate->r6);
  300. }
  301.  
  302. /** Interrupt Exception handler.
  303.  *
  304.  * Determines the sources of interrupt and calls their handlers.
  305.  */
  306. static void irq_exception(int exc_no, istate_t *istate)
  307. {
  308.     machine_irq_exception(exc_no, istate);
  309. }
  310.  
  311. /** Fills exception vectors with appropriate exception handlers. */
  312. void install_exception_handlers(void)
  313. {
  314.     install_handler((unsigned) reset_exception_entry,
  315.         (unsigned *) EXC_RESET_VEC);
  316.    
  317.     install_handler((unsigned) undef_instr_exception_entry,
  318.         (unsigned *) EXC_UNDEF_INSTR_VEC);
  319.    
  320.     install_handler((unsigned) swi_exception_entry,
  321.         (unsigned *) EXC_SWI_VEC);
  322.    
  323.     install_handler((unsigned) prefetch_abort_exception_entry,
  324.         (unsigned *) EXC_PREFETCH_ABORT_VEC);
  325.    
  326.     install_handler((unsigned) data_abort_exception_entry,
  327.         (unsigned *) EXC_DATA_ABORT_VEC);
  328.    
  329.     install_handler((unsigned) irq_exception_entry,
  330.         (unsigned *) EXC_IRQ_VEC);
  331.    
  332.     install_handler((unsigned)fiq_exception_entry,
  333.         (unsigned *) EXC_FIQ_VEC);
  334. }
  335.  
  336. #ifdef HIGH_EXCEPTION_VECTORS
  337. /** Activates use of high exception vectors addresses. */
  338. static void high_vectors(void)
  339. {
  340.     uint32_t control_reg;
  341.    
  342.     asm volatile (
  343.         "mrc p15, 0, %[control_reg], c1, c1"
  344.         : [control_reg] "=r" (control_reg)
  345.     );
  346.    
  347.     /* switch on the high vectors bit */
  348.     control_reg |= CP15_R1_HIGH_VECTORS_BIT;
  349.    
  350.     asm volatile (
  351.         "mcr p15, 0, %[control_reg], c1, c1"
  352.         :: [control_reg] "r" (control_reg)
  353.     );
  354. }
  355. #endif
  356.  
  357. /** Initializes exception handling.
  358.  *
  359.  * Installs low-level exception handlers and then registers
  360.  * exceptions and their handlers to kernel exception dispatcher.
  361.  */
  362. void exception_init(void)
  363. {
  364. #ifdef HIGH_EXCEPTION_VECTORS
  365.     high_vectors();
  366. #endif
  367.     install_exception_handlers();
  368.    
  369.     exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
  370.     exc_register(EXC_PREFETCH_ABORT, "prefetch abort",
  371.         (iroutine) prefetch_abort);
  372.     exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
  373.     exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
  374. }
  375.  
  376. /** Prints #istate_t structure content.
  377.  *
  378.  * @param istate Structure to be printed.
  379.  */
  380. void print_istate(istate_t *istate)
  381. {
  382.     dprintf("istate dump:\n");
  383.  
  384.     dprintf(" r0: %x    r1: %x    r2: %x    r3: %x\n",
  385.         istate->r0, istate->r1, istate->r2, istate->r3);
  386.     dprintf(" r4: %x    r5: %x    r6: %x    r7: %x\n",
  387.         istate->r4, istate->r5, istate->r6, istate->r7);
  388.     dprintf(" r8: %x    r8: %x   r10: %x   r11: %x\n",
  389.         istate->r8, istate->r9, istate->r10, istate->r11);
  390.     dprintf(" r12: %x    sp: %x    lr: %x  spsr: %x\n",
  391.         istate->r12, istate->sp, istate->lr, istate->spsr);
  392.  
  393.     dprintf(" pc: %x\n", istate->pc);
  394. }
  395.  
  396. /** @}
  397.  */
  398.