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  1. /*
  2.  * Copyright (c) 2007 Petr Stepan
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup arm32
  30.  * @{
  31.  */
  32. /** @file
  33.  *  @brief Exception handlers and exception initialization routines.
  34.  */
  35.  
  36. #include <arch/exception.h>
  37. #include <arch/memstr.h>
  38. #include <arch/regutils.h>
  39. #include <interrupt.h>
  40. #include <arch/mm/page_fault.h>
  41. #include <arch/barrier.h>
  42. #include <arch/machine.h>
  43. #include <print.h>
  44. #include <syscall/syscall.h>
  45.  
  46. /** Offset used in calculation of exception handler's relative address.
  47.  *
  48.  * @see install_handler()
  49.  */
  50. #define PREFETCH_OFFSET      0x8
  51.  
  52. /** LDR instruction's code */
  53. #define LDR_OPCODE           0xe59ff000
  54.  
  55. /** Number of exception vectors. */
  56. #define EXC_VECTORS          8
  57.  
  58. /** Size of memory block occupied by exception vectors. */
  59. #define EXC_VECTORS_SIZE     (EXC_VECTORS * 4)
  60.  
  61. /** Switches to kernel stack and saves all registers there.
  62.  *
  63.  * Temporary exception stack is used to save a few registers
  64.  * before stack switch takes place.
  65.  *
  66.  *  The stack fram created by the function looks like:
  67.  *
  68.  *      |_________________|
  69.  *      |                 |
  70.  *      |     SPSR        |
  71.  *      |                 |
  72.  *      |_________________|
  73.  *      | Stack Pointer   |
  74.  *      |      of         |
  75.  *      | Previous Mode   |
  76.  *      |_________________|
  77.  *      | Return address  |
  78.  *      |      of         |
  79.  *      | Previous Mode   |
  80.  *      |_________________|
  81.  *      |   R0  - R12     |
  82.  *      |      of         |
  83.  *      | Previous Mode   |
  84.  *      |_________________|
  85.  *      | Return address  |
  86.  *      |     from        |
  87.  *      |Exception Handler|
  88.  *      |_________________|
  89.  *      |                 |
  90.  *
  91.  */
  92. inline static void setup_stack_and_save_regs()
  93. {
  94.     asm volatile (
  95.         "ldr r13, =exc_stack\n"
  96.         "stmfd r13!, {r0-r3}\n"
  97.         "mrs r1, cpsr\n"
  98.         "bic r1, r1, #0x1f\n"
  99.         "mrs r2, spsr\n"
  100.         "and r0, r2, #0x1f\n"
  101.         "cmp r0, #0x10\n"
  102.         "bne 1f\n"
  103.        
  104.         /* prev mode was usermode */
  105.         "mov r0, sp\n"
  106.         "mov r3, lr\n"
  107.  
  108.         /* Switch to supervisor mode */
  109.         "orr r1, r1, #0x13\n"
  110.         "msr cpsr_c, r1\n"
  111.  
  112.         /* Load sp with [supervisor_sp] */
  113.         "ldr r13, =supervisor_sp\n"
  114.         "ldr r13, [r13]\n"
  115.  
  116.         /* Populate the stack frame */
  117.         "msr spsr, r2\n"
  118.         "mov lr, r3\n"
  119.         "stmfd r13!, {lr}\n"
  120.         "stmfd r13!, {r4-r12}\n"
  121.         "ldmfd r0!, {r4-r7}\n"
  122.         "stmfd r13!, {r4-r7}\n"
  123.         "stmfd r13!, {r13, lr}^\n"
  124.         "stmfd r13!, {r2}\n"
  125.         "b 2f\n"
  126.  
  127.    
  128.         /* mode was not usermode */
  129.         "1:\n"
  130.             /* Switch to previous mode which is undoubtedly the supervisor mode */
  131.             "orr r1, r1, r0\n"
  132.             "mov r0, lr\n"
  133.             "mov r3, sp\n"
  134.             "msr cpsr_c, r1\n"
  135.  
  136.             /* Populate the stack frame */
  137.             "mov r1, sp\n"
  138.             "stmfd r13!, {r0}\n"
  139.             "stmfd r13!, {r4-r12}\n"
  140.  
  141.             /* Store r0-r3 in r4-r7 and then push it on to stack */
  142.             "ldmfd r3!, {r4-r7}\n"
  143.             "stmfd r13!, {r4-r7}\n"
  144.  
  145.             /* Push return address and stack pointer on to stack */
  146.             "stmfd r13!, {lr}\n"
  147.             "stmfd r13!, {r1}\n"
  148.             "mov lr, r0\n"
  149.             "msr spsr, r2\n"
  150.             "stmfd r13!, {r2}\n"
  151.  
  152.         "2:\n"
  153.     );
  154. }
  155.  
  156. /** Returns from exception mode.
  157.  *
  158.  * Previously saved state of registers (including control register)
  159.  * is restored from the stack.
  160.  */
  161. inline static void load_regs()
  162. {
  163.     asm volatile(
  164.         "ldmfd r13!, {r0}       \n"
  165.         "msr spsr, r0           \n"
  166.         "and r0, r0, #0x1f      \n"
  167.         "cmp r0, #0x10          \n"
  168.         "bne 1f             \n"
  169.  
  170.         /* return to user mode */
  171.         "ldmfd r13!, {r13, lr}^     \n"
  172.         "b 2f               \n"
  173.  
  174.         /* return to non-user mode */
  175.     "1:\n"
  176.         "ldmfd r13!, {r1, r2}       \n"
  177.         "mrs r3, cpsr           \n"
  178.         "bic r3, r3, #0x1f      \n"
  179.         "orr r3, r3, r0         \n"
  180.         "mrs r0, cpsr           \n"
  181.         "msr cpsr_c, r3         \n"
  182.  
  183.         "mov lr, r2         \n"
  184.         "msr cpsr_c, r0         \n"
  185.  
  186.         /* actual return */
  187.     "2:\n"
  188.         "ldmfd r13!, {r0-r12, pc}^\n"
  189.     );
  190. }
  191.  
  192.  
  193. /** Calls exception dispatch routine. */
  194. #define CALL_EXC_DISPATCH(exception) \
  195.     asm volatile ( \
  196.         "mov r0, %[exc]\n" \
  197.         "mov r1, r13\n" \
  198.         "bl exc_dispatch\n" \
  199.         :: [exc] "i" (exception) \
  200.     );\
  201.  
  202. /** General exception handler.
  203.  *
  204.  *  Stores registers, dispatches the exception,
  205.  *  and finally restores registers and returns from exception processing.
  206.  *
  207.  *  @param exception Exception number.
  208.  */
  209. #define PROCESS_EXCEPTION(exception) \
  210.     setup_stack_and_save_regs(); \
  211.     CALL_EXC_DISPATCH(exception) \
  212.     load_regs();
  213.  
  214. /** Updates specified exception vector to jump to given handler.
  215.  *
  216.  *  Addresses of handlers are stored in memory following exception vectors.
  217.  */
  218. static void install_handler(unsigned handler_addr, unsigned *vector)
  219. {
  220.     /* relative address (related to exc. vector) of the word
  221.      * where handler's address is stored
  222.     */
  223.     volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -
  224.         PREFETCH_OFFSET;
  225.    
  226.     /* make it LDR instruction and store at exception vector */
  227.     *vector = handler_address_ptr | LDR_OPCODE;
  228.     smc_coherence(*vector);
  229.    
  230.     /* store handler's address */
  231.     *(vector + EXC_VECTORS) = handler_addr;
  232.  
  233. }
  234.  
  235. /** Low-level Reset Exception handler. */
  236. static void reset_exception_entry(void)
  237. {
  238.     PROCESS_EXCEPTION(EXC_RESET);
  239. }
  240.  
  241. /** Low-level Software Interrupt Exception handler. */
  242. static void swi_exception_entry(void)
  243. {
  244.     PROCESS_EXCEPTION(EXC_SWI);
  245. }
  246.  
  247. /** Low-level Undefined Instruction Exception handler. */
  248. static void undef_instr_exception_entry(void)
  249. {
  250.     PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
  251. }
  252.  
  253. /** Low-level Fast Interrupt Exception handler. */
  254. static void fiq_exception_entry(void)
  255. {
  256.     PROCESS_EXCEPTION(EXC_FIQ);
  257. }
  258.  
  259. /** Low-level Prefetch Abort Exception handler. */
  260. static void prefetch_abort_exception_entry(void)
  261. {
  262.     asm volatile (
  263.         "sub lr, lr, #4"
  264.     );
  265.    
  266.     PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
  267. }
  268.  
  269. /** Low-level Data Abort Exception handler. */
  270. static void data_abort_exception_entry(void)
  271. {
  272.     asm volatile (
  273.         "sub lr, lr, #8"
  274.     );
  275.    
  276.     PROCESS_EXCEPTION(EXC_DATA_ABORT);
  277. }
  278.  
  279. /** Low-level Interrupt Exception handler.
  280.  *
  281.  * CPU is switched to Undefined mode before further interrupt processing
  282.  * because of possible occurence of nested interrupt exception, which
  283.  * would overwrite (and thus spoil) stack pointer.
  284.  */
  285. static void irq_exception_entry(void)
  286. {
  287.     asm volatile (
  288.         "sub lr, lr, #4"
  289.     );
  290.    
  291.     PROCESS_EXCEPTION(EXC_IRQ)
  292. }
  293.  
  294. /** Software Interrupt handler.
  295.  *
  296.  * Dispatches the syscall.
  297.  */
  298. static void swi_exception(int exc_no, istate_t *istate)
  299. {
  300.     istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2,
  301.         istate->r3, istate->r4, istate->r5, istate->r6);
  302. }
  303.  
  304. /** Fills exception vectors with appropriate exception handlers. */
  305. void install_exception_handlers(void)
  306. {
  307.     install_handler((unsigned) reset_exception_entry,
  308.         (unsigned *) EXC_RESET_VEC);
  309.    
  310.     install_handler((unsigned) undef_instr_exception_entry,
  311.         (unsigned *) EXC_UNDEF_INSTR_VEC);
  312.    
  313.     install_handler((unsigned) swi_exception_entry,
  314.         (unsigned *) EXC_SWI_VEC);
  315.    
  316.     install_handler((unsigned) prefetch_abort_exception_entry,
  317.         (unsigned *) EXC_PREFETCH_ABORT_VEC);
  318.    
  319.     install_handler((unsigned) data_abort_exception_entry,
  320.         (unsigned *) EXC_DATA_ABORT_VEC);
  321.    
  322.     install_handler((unsigned) irq_exception_entry,
  323.         (unsigned *) EXC_IRQ_VEC);
  324.    
  325.     install_handler((unsigned) fiq_exception_entry,
  326.         (unsigned *) EXC_FIQ_VEC);
  327. }
  328.  
  329. #ifdef HIGH_EXCEPTION_VECTORS
  330. /** Activates use of high exception vectors addresses. */
  331. static void high_vectors(void)
  332. {
  333.     uint32_t control_reg;
  334.    
  335.     asm volatile (
  336.         "mrc p15, 0, %[control_reg], c1, c1"
  337.         : [control_reg] "=r" (control_reg)
  338.     );
  339.    
  340.     /* switch on the high vectors bit */
  341.     control_reg |= CP15_R1_HIGH_VECTORS_BIT;
  342.    
  343.     asm volatile (
  344.         "mcr p15, 0, %[control_reg], c1, c1"
  345.         :: [control_reg] "r" (control_reg)
  346.     );
  347. }
  348. #endif
  349.  
  350. /** Interrupt Exception handler.
  351.  *
  352.  * Determines the sources of interrupt and calls their handlers.
  353.  */
  354. static void irq_exception(int exc_no, istate_t *istate)
  355. {
  356.     machine_irq_exception(exc_no, istate);
  357. }
  358.  
  359. /** Initializes exception handling.
  360.  *
  361.  * Installs low-level exception handlers and then registers
  362.  * exceptions and their handlers to kernel exception dispatcher.
  363.  */
  364. void exception_init(void)
  365. {
  366. #ifdef HIGH_EXCEPTION_VECTORS
  367.     high_vectors();
  368. #endif
  369.     install_exception_handlers();
  370.    
  371.     exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
  372.     exc_register(EXC_PREFETCH_ABORT, "prefetch abort",
  373.         (iroutine) prefetch_abort);
  374.     exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
  375.     exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
  376. }
  377.  
  378. /** Prints #istate_t structure content.
  379.  *
  380.  * @param istate Structure to be printed.
  381.  */
  382. void print_istate(istate_t *istate)
  383. {
  384.     printf("istate dump:\n");
  385.    
  386.     printf(" r0: %x    r1: %x    r2: %x    r3: %x\n",
  387.         istate->r0, istate->r1, istate->r2, istate->r3);
  388.     printf(" r4: %x    r5: %x    r6: %x    r7: %x\n",
  389.         istate->r4, istate->r5, istate->r6, istate->r7);
  390.     printf(" r8: %x    r8: %x   r10: %x   r11: %x\n",
  391.         istate->r8, istate->r9, istate->r10, istate->r11);
  392.     printf(" r12: %x    sp: %x    lr: %x  spsr: %x\n",
  393.         istate->r12, istate->sp, istate->lr, istate->spsr);
  394.    
  395.     printf(" pc: %x\n", istate->pc);
  396. }
  397.  
  398. /** @}
  399.  */
  400.