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  1. /*
  2.  * Copyright (c) 2007 Petr Stepan
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup arm32
  30.  * @{
  31.  */
  32. /** @file
  33.  *  @brief Exception handlers and exception initialization routines.
  34.  */
  35.  
  36. #include <arch/exception.h>
  37. #include <arch/debug/print.h>
  38. #include <arch/memstr.h>
  39. #include <arch/regutils.h>
  40. #include <interrupt.h>
  41. #include <arch/machine.h>
  42. #include <arch/mm/page_fault.h>
  43. #include <print.h>
  44. #include <syscall/syscall.h>
  45.  
  46. /** Offset used in calculation of exception handler's relative address.
  47.  *
  48.  * @see install_handler()
  49.  */
  50. #define PREFETCH_OFFSET      0x8
  51.  
  52. /** LDR instruction's code */
  53. #define LDR_OPCODE           0xe59ff000
  54.  
  55. /** Number of exception vectors. */
  56. #define EXC_VECTORS          8
  57.  
  58. /** Size of memory block occupied by exception vectors. */
  59. #define EXC_VECTORS_SIZE     (EXC_VECTORS * 4)
  60.  
  61. /** Switches to kernel stack and saves all registers there.
  62.  *
  63.  * Temporary exception stack is used to save a few registers
  64.  * before stack switch takes place.
  65.  */
  66. inline static void setup_stack_and_save_regs()
  67. {
  68.     asm volatile(
  69.         "ldr r13, =exc_stack        \n"
  70.         "stmfd r13!, {r0}       \n"
  71.         "mrs r0, spsr           \n"
  72.         "and r0, r0, #0x1f      \n"
  73.         "cmp r0, #0x10          \n"
  74.         "bne 1f             \n"
  75.  
  76.         /* prev mode was usermode */
  77.         "ldmfd r13!, {r0}       \n"
  78.         "ldr r13, =supervisor_sp    \n"
  79.         "ldr r13, [r13]         \n"
  80.         "stmfd r13!, {lr}       \n"
  81.         "stmfd r13!, {r0-r12}       \n"
  82.         "stmfd r13!, {r13, lr}^     \n"
  83.         "mrs r0, spsr           \n"
  84.         "stmfd r13!, {r0}       \n"
  85.         "b 2f               \n"
  86.  
  87.         /* mode was not usermode */
  88.     "1:\n"
  89.         "stmfd r13!, {r1, r2, r3}   \n"
  90.         "mrs r1, cpsr           \n"
  91.         "mov r2, lr         \n"
  92.         "bic r1, r1, #0x1f      \n"
  93.         "orr r1, r1, r0         \n"
  94.         "mrs r0, cpsr           \n"
  95.         "msr cpsr_c, r1         \n"
  96.  
  97.         "mov r3, r13            \n"
  98.         "stmfd r13!, {r2}       \n"
  99.         "mov r2, lr         \n"
  100.         "stmfd r13!, {r4-r12}       \n"
  101.         "mov r1, r13            \n"
  102.         /* the following two lines are for debugging */
  103.         "mov sp, #0         \n"
  104.         "mov lr, #0         \n"
  105.         "msr cpsr_c, r0         \n"
  106.  
  107.         "ldmfd r13!, {r4, r5, r6, r7}   \n"
  108.         "stmfd r1!, {r4, r5, r6}    \n"
  109.         "stmfd r1!, {r7}        \n"
  110.         "stmfd r1!, {r2}        \n"
  111.         "stmfd r1!, {r3}        \n"
  112.         "mrs r0, spsr           \n"
  113.         "stmfd r1!, {r0}        \n"
  114.         "mov r13, r1            \n"
  115.     "2:\n"
  116.     );
  117. }
  118.  
  119. /** Returns from exception mode.
  120.  *
  121.  * Previously saved state of registers (including control register)
  122.  * is restored from the stack.
  123.  */
  124. inline static void load_regs()
  125. {
  126.     asm volatile(
  127.         "ldmfd r13!, {r0}       \n"
  128.         "msr spsr, r0           \n"
  129.         "and r0, r0, #0x1f      \n"
  130.         "cmp r0, #0x10          \n"
  131.         "bne 1f             \n"
  132.  
  133.         /* return to user mode */
  134.         "ldmfd r13!, {r13, lr}^     \n"
  135.         "b 2f               \n"
  136.  
  137.         /* return to non-user mode */
  138.     "1:\n"
  139.         "ldmfd r13!, {r1, r2}       \n"
  140.         "mrs r3, cpsr           \n"
  141.         "bic r3, r3, #0x1f      \n"
  142.         "orr r3, r3, r0         \n"
  143.         "mrs r0, cpsr           \n"
  144.         "msr cpsr_c, r3         \n"
  145.  
  146.         "mov r13, r1            \n"
  147.         "mov lr, r2         \n"
  148.         "msr cpsr_c, r0         \n"
  149.  
  150.         /* actual return */
  151.     "2:\n"
  152.         "ldmfd r13, {r0-r12, pc}^\n"
  153.     );
  154. }
  155.  
  156.  
  157. /** Switch CPU to mode in which interrupts are serviced (currently it
  158.  * is Undefined mode).
  159.  *
  160.  * The default mode for interrupt servicing (Interrupt Mode)
  161.  * can not be used because of nested interrupts (which can occur
  162.  * because interrupts are enabled in higher levels of interrupt handler).
  163.  */
  164. inline static void switch_to_irq_servicing_mode()
  165. {
  166.     /* switch to Undefined mode */
  167.     asm volatile(
  168.         /* save regs used during switching */
  169.         "stmfd sp!, {r0-r3}     \n"
  170.  
  171.         /* save stack pointer and link register to r1, r2 */
  172.         "mov r1, sp         \n"
  173.         "mov r2, lr         \n"
  174.  
  175.         /* mode switch */
  176.         "mrs r0, cpsr           \n"
  177.         "bic r0, r0, #0x1f      \n"
  178.         "orr r0, r0, #0x1b      \n"
  179.         "msr cpsr_c, r0         \n"
  180.  
  181.         /* restore saved sp and lr */
  182.         "mov sp, r1         \n"
  183.         "mov lr, r2         \n"
  184.  
  185.         /* restore original regs */
  186.         "ldmfd sp!, {r0-r3}     \n"
  187.     );
  188. }
  189.  
  190. /** Calls exception dispatch routine. */
  191. #define CALL_EXC_DISPATCH(exception)        \
  192.     asm("mov r0, %0" : : "i" (exception));  \
  193.     asm("mov r1, r13");         \
  194.     asm("bl exc_dispatch");    
  195.  
  196. /** General exception handler.
  197.  *
  198.  *  Stores registers, dispatches the exception,
  199.  *  and finally restores registers and returns from exception processing.
  200.  *
  201.  *  @param exception Exception number.
  202.  */
  203. #define PROCESS_EXCEPTION(exception)        \
  204.     setup_stack_and_save_regs();        \
  205.     CALL_EXC_DISPATCH(exception)        \
  206.     load_regs();
  207.  
  208. /** Updates specified exception vector to jump to given handler.
  209.  *
  210.  *  Addresses of handlers are stored in memory following exception vectors.
  211.  */
  212. static void install_handler (unsigned handler_addr, unsigned* vector)
  213. {
  214.     /* relative address (related to exc. vector) of the word
  215.      * where handler's address is stored
  216.     */
  217.     volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET;
  218.    
  219.     /* make it LDR instruction and store at exception vector */
  220.     *vector = handler_address_ptr | LDR_OPCODE;
  221.    
  222.     /* store handler's address */
  223.     *(vector + EXC_VECTORS) = handler_addr;
  224.  
  225. }
  226.  
  227. /** Low-level Reset Exception handler. */
  228. static void reset_exception_entry()
  229. {
  230.     PROCESS_EXCEPTION(EXC_RESET);
  231. }
  232.  
  233. /** Low-level Software Interrupt Exception handler. */
  234. static void swi_exception_entry()
  235. {
  236.     PROCESS_EXCEPTION(EXC_SWI);
  237. }
  238.  
  239. /** Low-level Undefined Instruction Exception handler. */
  240. static void undef_instr_exception_entry()
  241. {
  242.     PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
  243. }
  244.  
  245. /** Low-level Fast Interrupt Exception handler. */
  246. static void fiq_exception_entry()
  247. {
  248.     PROCESS_EXCEPTION(EXC_FIQ);
  249. }
  250.  
  251. /** Low-level Prefetch Abort Exception handler. */
  252. static void prefetch_abort_exception_entry()
  253. {
  254.     asm("sub lr, lr, #4");
  255.     PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
  256. }
  257.  
  258. /** Low-level Data Abort Exception handler. */
  259. static void data_abort_exception_entry()
  260. {
  261.     asm("sub lr, lr, #8");
  262.     PROCESS_EXCEPTION(EXC_DATA_ABORT);
  263. }
  264.  
  265. /** Low-level Interrupt Exception handler.
  266.  *
  267.  * CPU is switched to Undefined mode before further interrupt processing
  268.  * because of possible occurence of nested interrupt exception, which
  269.  * would overwrite (and thus spoil) stack pointer.
  270.  */
  271. static void irq_exception_entry()
  272. {
  273.     asm("sub lr, lr, #4");
  274.     setup_stack_and_save_regs();
  275.    
  276.     switch_to_irq_servicing_mode();
  277.    
  278.     CALL_EXC_DISPATCH(EXC_IRQ)
  279.  
  280.     load_regs();
  281. }
  282.  
  283. /** Software Interrupt handler.
  284.  *
  285.  * Dispatches the syscall.
  286.  */
  287. static void swi_exception(int exc_no, istate_t *istate)
  288. {
  289.     /*
  290.     dprintf("SYSCALL: r0-r4: %x, %x, %x, %x, %x; pc: %x\n", istate->r0,
  291.         istate->r1, istate->r2, istate->r3, istate->r4, istate->pc);
  292.     */
  293.  
  294.     istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2,
  295.         istate->r3, istate->r4);
  296. }
  297.  
  298. /** Interrupt Exception handler.
  299.  *
  300.  * Determines the sources of interrupt and calls their handlers.
  301.  */
  302. static void irq_exception(int exc_no, istate_t *istate)
  303. {
  304.     machine_irq_exception(exc_no, istate);
  305. }
  306.  
  307. /** Fills exception vectors with appropriate exception handlers. */
  308. void install_exception_handlers(void)
  309. {
  310.     install_handler((unsigned) reset_exception_entry,
  311.         (unsigned *) EXC_RESET_VEC);
  312.    
  313.     install_handler((unsigned) undef_instr_exception_entry,
  314.         (unsigned *) EXC_UNDEF_INSTR_VEC);
  315.    
  316.     install_handler((unsigned) swi_exception_entry,
  317.         (unsigned *) EXC_SWI_VEC);
  318.    
  319.     install_handler((unsigned) prefetch_abort_exception_entry,
  320.         (unsigned *) EXC_PREFETCH_ABORT_VEC);
  321.    
  322.     install_handler((unsigned) data_abort_exception_entry,
  323.         (unsigned *) EXC_DATA_ABORT_VEC);
  324.    
  325.     install_handler((unsigned) irq_exception_entry,
  326.         (unsigned *) EXC_IRQ_VEC);
  327.    
  328.     install_handler((unsigned)fiq_exception_entry,
  329.         (unsigned *) EXC_FIQ_VEC);
  330. }
  331.  
  332. #ifdef HIGH_EXCEPTION_VECTORS
  333. /** Activates use of high exception vectors addresses. */
  334. static void high_vectors(void)
  335. {
  336.     uint32_t control_reg;
  337.    
  338.     asm volatile("mrc p15, 0, %0, c1, c1" : "=r" (control_reg));
  339.    
  340.     /* switch on the high vectors bit */
  341.     control_reg |= CP15_R1_HIGH_VECTORS_BIT;
  342.    
  343.     asm volatile("mcr p15, 0, %0, c1, c1" : : "r" (control_reg));
  344. }
  345. #endif
  346.  
  347. /** Initializes exception handling.
  348.  *
  349.  * Installs low-level exception handlers and then registers
  350.  * exceptions and their handlers to kernel exception dispatcher.
  351.  */
  352. void exception_init(void)
  353. {
  354. #ifdef HIGH_EXCEPTION_VECTORS
  355.     high_vectors();
  356. #endif
  357.     install_exception_handlers();
  358.    
  359.     exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
  360.     exc_register(EXC_PREFETCH_ABORT, "prefetch abort",
  361.         (iroutine) prefetch_abort);
  362.     exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
  363.     exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
  364. }
  365.  
  366. /** Prints #istate_t structure content.
  367.  *
  368.  * @param istate Structure to be printed.
  369.  */
  370. void print_istate(istate_t *istate)
  371. {
  372.     dprintf("istate dump:\n");
  373.  
  374.     dprintf(" r0: %x    r1: %x    r2: %x    r3: %x\n",
  375.         istate->r0, istate->r1, istate->r2, istate->r3);
  376.     dprintf(" r4: %x    r5: %x    r6: %x    r7: %x\n",
  377.         istate->r4, istate->r5, istate->r6, istate->r7);
  378.     dprintf(" r8: %x    r8: %x   r10: %x   r11: %x\n",
  379.         istate->r8, istate->r9, istate->r10, istate->r11);
  380.     dprintf(" r12: %x    sp: %x    lr: %x  spsr: %x\n",
  381.         istate->r12, istate->sp, istate->lr, istate->spsr);
  382.  
  383.     dprintf(" pc: %x\n", istate->pc);
  384. }
  385.  
  386. /** @}
  387.  */
  388.