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  1. /*
  2.  * Copyright (c) 2007 Michal Kebrt, Petr Stepan
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup arm32qemu_icp
  30.  * @{
  31.  */
  32. /** @file
  33.  *  @brief QEMU icp drivers.
  34.  */
  35.  
  36. #include <interrupt.h>
  37. #include <ipc/irq.h>
  38. #include <console/chardev.h>
  39. #include <arch/drivers/qemu.h>
  40. #include <console/console.h>
  41. #include <sysinfo/sysinfo.h>
  42. #include <print.h>
  43. #include <ddi/device.h>
  44. #include <mm/page.h>
  45. #include <arch/machine.h>
  46. #include <arch/debug/print.h>
  47. #include <genarch/fb/fb.h>
  48. #include <genarch/fb/visuals.h>
  49.  
  50. /* Addresses of devices. */
  51. #define QEMU_ICP_VIDEORAM            0x16000000
  52. #define QEMU_ICP_KBD                 0x18000000
  53. #define QEMU_ICP_HALT_OFFSET         0x10
  54. #define QEMU_ICP_RTC                 0x13000000
  55. #define QEMU_ICP_RTC_FREQ_OFFSET     0x100
  56. #define QEMU_ICP_RTC_ACK_OFFSET      0x110
  57. #define QEMU_ICP_IRQC                0x14000000
  58. #define QEMU_ICP_IRQC_MASK_OFFSET    0xC
  59. #define QEMU_ICP_IRQC_UNMASK_OFFSET  0x8
  60. #define QEMU_ICP_MP                  0x11000000
  61. #define QEMU_ICP_MP_MEMSIZE_OFFSET   0x0090
  62. #define QEMU_ICP_FB                  0x94000
  63.  
  64. #define ICP_VGA              0xC0000000
  65. #define ICP_CMCR             0x10000000
  66.  
  67. /* IRQs */
  68. #define QEMU_ICP_KBD_IRQ        0x03
  69. #define QEMU_ICP_TIMER_IRQ      0x05
  70.  
  71. static qemu_icp_hw_map_t qemu_icp_hw_map;
  72. static chardev_t console;
  73. static irq_t qemu_icp_console_irq;
  74. static irq_t qemu_icp_timer_irq;
  75.  
  76. static bool hw_map_init_called = false;
  77. static bool vga_init = false;
  78.  
  79. static void qemu_icp_kbd_enable(chardev_t *dev);
  80. static void qemu_icp_kbd_disable(chardev_t *dev);
  81. static void qemu_icp_write(chardev_t *dev, const char ch);
  82. static char qemu_icp_do_read(chardev_t *dev);
  83. void icp_vga_init(void);
  84.  
  85. static chardev_operations_t qemu_icp_ops = {
  86.     .resume = qemu_icp_kbd_enable,
  87.     .suspend = qemu_icp_kbd_disable,
  88.     .write = qemu_icp_write,
  89.     .read = qemu_icp_do_read,
  90. };
  91.  
  92. /** Initializes the vga
  93.  *
  94.  */
  95. void icp_vga_init(void)
  96. {
  97.     *(uint32_t*)((char *)(qemu_icp_hw_map.cmcr)+0x14) = 0xA05F0000;
  98.     *(uint32_t*)((char *)(qemu_icp_hw_map.cmcr)+0x1C) = 0x12C11000;
  99.     *(uint32_t*)qemu_icp_hw_map.vga = 0x3F1F3F9C;
  100.     *(uint32_t*)((char *)(qemu_icp_hw_map.vga) + 0x4) = 0x080B61DF;
  101.     *(uint32_t*)((char *)(qemu_icp_hw_map.vga) + 0x8) = 0x067F3800;
  102.     *(uint32_t*)((char *)(qemu_icp_hw_map.vga) + 0x10) = QEMU_ICP_FB;
  103.     *(uint32_t *)((char *)(qemu_icp_hw_map.vga) + 0x1C) = 0x182B;
  104.     *(uint32_t*)((char *)(qemu_icp_hw_map.cmcr)+0xC) = 0x33805000;
  105.    
  106. }
  107.  
  108. /** Returns the mask of active interrupts. */
  109. static inline uint32_t qemu_icp_irqc_get_sources(void)
  110. {
  111.     return *((uint32_t *) qemu_icp_hw_map.irqc);
  112. }
  113.  
  114.  
  115. /** Masks interrupt.
  116.  *
  117.  * @param irq interrupt number
  118.  */
  119. static inline void qemu_icp_irqc_mask(uint32_t irq)
  120. {
  121.     *((uint32_t *) qemu_icp_hw_map.irqc_mask) = irq;
  122. }
  123.  
  124.  
  125. /** Unmasks interrupt.
  126.  *
  127.  * @param irq interrupt number
  128.  */
  129. static inline void qemu_icp_irqc_unmask(uint32_t irq)
  130. {
  131.     *((uint32_t *) qemu_icp_hw_map.irqc_unmask) |= irq;
  132. }
  133.  
  134. /** Initializes the icp frame buffer */
  135. void qemu_icp_fb_init(void)
  136. {
  137.     fb_init(qemu_icp_get_fb_address(), 640, 480, 2560, VISUAL_BGR_8_8_8_0);
  138. }
  139.  
  140. /** Initializes #qemu_icp_hw_map. */
  141. void qemu_icp_hw_map_init(void)
  142. {
  143.     qemu_icp_hw_map.videoram = hw_map(QEMU_ICP_VIDEORAM, PAGE_SIZE);
  144.     qemu_icp_hw_map.kbd = hw_map(QEMU_ICP_KBD, PAGE_SIZE);
  145.     qemu_icp_hw_map.rtc = hw_map(QEMU_ICP_RTC, PAGE_SIZE);
  146.     qemu_icp_hw_map.irqc = hw_map(QEMU_ICP_IRQC, PAGE_SIZE);
  147.  
  148.     qemu_icp_hw_map.rtc_freq = qemu_icp_hw_map.rtc + QEMU_ICP_RTC_FREQ_OFFSET;
  149.     qemu_icp_hw_map.rtc_ack = qemu_icp_hw_map.rtc + QEMU_ICP_RTC_ACK_OFFSET;
  150.     qemu_icp_hw_map.irqc_mask = qemu_icp_hw_map.irqc + QEMU_ICP_IRQC_MASK_OFFSET;
  151.     qemu_icp_hw_map.irqc_unmask = qemu_icp_hw_map.irqc +
  152.         QEMU_ICP_IRQC_UNMASK_OFFSET;
  153.     qemu_icp_hw_map.cmcr = hw_map(ICP_CMCR, PAGE_SIZE);
  154.     qemu_icp_hw_map.vga = hw_map(ICP_VGA, PAGE_SIZE);
  155.  
  156.     //icp_vga_init();
  157.  
  158.     hw_map_init_called = true;
  159. }
  160.  
  161.  
  162. /** Putchar that works with qemu_icp.
  163.  *
  164.  * @param dev Not used.
  165.  * @param ch Characted to be printed.
  166.  */
  167. static void qemu_icp_write(chardev_t *dev, const char ch)
  168. {
  169.     *((char *) qemu_icp_hw_map.videoram) = ch;
  170. }
  171.  
  172. /** Enables qemu_icp keyboard (interrupt unmasked).
  173.  *
  174.  * @param dev Not used.
  175.  *
  176.  * Called from getc().
  177.  */
  178. static void qemu_icp_kbd_enable(chardev_t *dev)
  179. {
  180.     qemu_icp_irqc_unmask(QEMU_ICP_KBD_IRQ);
  181. }
  182.  
  183. /** Disables qemu_icp keyboard (interrupt masked).
  184.  *
  185.  * @param dev not used
  186.  *
  187.  * Called from getc().
  188.  */
  189. static void qemu_icp_kbd_disable(chardev_t *dev)
  190. {
  191.     qemu_icp_irqc_mask(QEMU_ICP_KBD_IRQ);
  192. }
  193.  
  194. /** Read character using polling, assume interrupts disabled.
  195.  *
  196.  *  @param dev Not used.
  197.  */
  198. static char qemu_icp_do_read(chardev_t *dev)
  199. {
  200.     char ch;
  201.  
  202.     while (1) {
  203.         ch = *((volatile char *) qemu_icp_hw_map.kbd);
  204.         if (ch) {
  205.             if (ch == '\r')
  206.                 return '\n';
  207.             if (ch == 0x7f)
  208.                 return '\b';
  209.             return ch;
  210.         }
  211.     }
  212. }
  213.  
  214. /** Process keyboard interrupt.
  215.  *  
  216.  *  @param irq IRQ information.
  217.  *  @param arg Not used.
  218.  */
  219. static void qemu_icp_irq_handler(irq_t *irq, void *arg, ...)
  220. {
  221.     if ((irq->notif_cfg.notify) && (irq->notif_cfg.answerbox)) {
  222.         ipc_irq_send_notif(irq);
  223.     } else {
  224.         char ch = 0;
  225.        
  226.         ch = *((char *) qemu_icp_hw_map.kbd);
  227.         if (ch == '\r') {
  228.             ch = '\n';
  229.         }
  230.         if (ch == 0x7f) {
  231.             ch = '\b';
  232.         }
  233.         chardev_push_character(&console, ch);
  234.     }
  235. }
  236.  
  237. static irq_ownership_t qemu_icp_claim(void)
  238. {
  239.     return IRQ_ACCEPT;
  240. }
  241.  
  242.  
  243. /** Acquire console back for kernel. */
  244. void qemu_icp_grab_console(void)
  245. {
  246.     ipl_t ipl = interrupts_disable();
  247.     spinlock_lock(&qemu_icp_console_irq.lock);
  248.     qemu_icp_console_irq.notif_cfg.notify = false;
  249.     spinlock_unlock(&qemu_icp_console_irq.lock);
  250.     interrupts_restore(ipl);
  251. }
  252.  
  253. /** Return console to userspace. */
  254. void qemu_icp_release_console(void)
  255. {
  256.     ipl_t ipl = interrupts_disable();
  257.     spinlock_lock(&qemu_icp_console_irq.lock);
  258.     if (qemu_icp_console_irq.notif_cfg.answerbox) {
  259.         qemu_icp_console_irq.notif_cfg.notify = true;
  260.     }
  261.     spinlock_unlock(&qemu_icp_console_irq.lock);
  262.     interrupts_restore(ipl);
  263. }
  264.  
  265. /** Initializes console object representing qemu_icp console.
  266.  *
  267.  *  @param devno device number.
  268.  */
  269. void qemu_icp_console_init(devno_t devno)
  270. {
  271.     chardev_initialize("qemu_icp_console", &console, &qemu_icp_ops);
  272.     stdin = &console;
  273.     stdout = &console;
  274.    
  275.     irq_initialize(&qemu_icp_console_irq);
  276.     qemu_icp_console_irq.devno = devno;
  277.     qemu_icp_console_irq.inr = QEMU_ICP_KBD_IRQ;
  278.     qemu_icp_console_irq.claim = qemu_icp_claim;
  279.     qemu_icp_console_irq.handler = qemu_icp_irq_handler;
  280.     irq_register(&qemu_icp_console_irq);
  281.    
  282.     qemu_icp_irqc_unmask(QEMU_ICP_KBD_IRQ);
  283.    
  284.     sysinfo_set_item_val("kbd", NULL, true);
  285.     sysinfo_set_item_val("kbd.devno", NULL, devno);
  286.     sysinfo_set_item_val("kbd.inr", NULL, QEMU_ICP_KBD_IRQ);
  287.     sysinfo_set_item_val("kbd.address.virtual", NULL, qemu_icp_hw_map.kbd);
  288. }
  289.  
  290. /** Starts qemu_icp Real Time Clock device, which asserts regular interrupts.
  291.  *
  292.  * @param frequency Interrupts frequency (0 disables RTC).
  293.  */
  294. static void qemu_icp_timer_start(uint32_t frequency)
  295. {
  296.     *((uint32_t*) qemu_icp_hw_map.rtc_freq) = frequency;
  297. }
  298.  
  299. static irq_ownership_t qemu_icp_timer_claim(void)
  300. {
  301.     return IRQ_ACCEPT;
  302. }
  303.  
  304. /** Timer interrupt handler.
  305.  *
  306.  * @param irq Interrupt information.
  307.  * @param arg Not used.
  308.  */
  309. static void qemu_icp_timer_irq_handler(irq_t *irq, void *arg, ...)
  310. {
  311.     /*
  312.     * We are holding a lock which prevents preemption.
  313.     * Release the lock, call clock() and reacquire the lock again.
  314.     */
  315.     spinlock_unlock(&irq->lock);
  316.     clock();
  317.     spinlock_lock(&irq->lock);
  318.  
  319.     /* acknowledge tick */
  320.     *((uint32_t*) qemu_icp_hw_map.rtc_ack) = 0;
  321. }
  322.  
  323. /** Initializes and registers timer interrupt handler. */
  324. static void qemu_icp_timer_irq_init(void)
  325. {
  326.     irq_initialize(&qemu_icp_timer_irq);
  327.     qemu_icp_timer_irq.devno = device_assign_devno();
  328.     qemu_icp_timer_irq.inr = QEMU_ICP_TIMER_IRQ;
  329.     qemu_icp_timer_irq.claim = qemu_icp_timer_claim;
  330.     qemu_icp_timer_irq.handler = qemu_icp_timer_irq_handler;
  331.  
  332.     irq_register(&qemu_icp_timer_irq);
  333. }
  334.  
  335.  
  336. /** Starts timer.
  337.  *
  338.  * Initiates regular timer interrupts after initializing
  339.  * corresponding interrupt handler.
  340.  */
  341. void qemu_icp_timer_irq_start(void)
  342. {
  343.     qemu_icp_timer_irq_init();
  344.     qemu_icp_timer_start(QEMU_ICP_TIMER_FREQ);
  345. }
  346.  
  347. /** Returns the size of emulated memory.
  348.  *
  349.  * @return Size in bytes.
  350.  */
  351. size_t qemu_icp_get_memory_size(void)
  352. {
  353.     //return  *((int *) (QEMU_ICP_MP + QEMU_ICP_MP_MEMSIZE_OFFSET));
  354.     return 0x2000000;
  355. }
  356.  
  357. /** Prints a character.
  358.  *
  359.  *  @param ch Character to be printed.
  360.  */
  361. void qemu_icp_debug_putc(char ch)
  362. {
  363.     char *addr = 0;
  364.     if (!hw_map_init_called) {
  365.         addr = (char *) QEMU_ICP_KBD;
  366.     } else {
  367.         addr = (char *) qemu_icp_hw_map.videoram;
  368.     }
  369.    
  370.     if (ch == '\n')
  371.         *(addr) = '\r';
  372.     *(addr) = ch;
  373. }
  374.  
  375. /** Stops qemu_icp. */
  376. void qemu_icp_cpu_halt(void)
  377. {
  378.     char * addr = 0;
  379.     if (!hw_map_init_called) {
  380.         addr = (char *) QEMU_ICP_KBD;
  381.     } else {
  382.         addr = (char *) qemu_icp_hw_map.videoram;
  383.     }
  384.    
  385.     *(addr + QEMU_ICP_HALT_OFFSET) = '\0';
  386. }
  387.  
  388. /** Gxemul specific interrupt exception handler.
  389.  *
  390.  * Determines sources of the interrupt from interrupt controller and
  391.  * calls high-level handlers for them.
  392.  *
  393.  * @param exc_no Interrupt exception number.
  394.  * @param istate Saved processor state.
  395.  */
  396. void qemu_icp_irq_exception(int exc_no, istate_t *istate)
  397. {
  398.     uint32_t sources = qemu_icp_irqc_get_sources();
  399.     int i;
  400.    
  401.     for (i = 0; i < QEMU_ICP_IRQC_MAX_IRQ; i++) {
  402.         if (sources & (1 << i)) {
  403.             irq_t *irq = irq_dispatch_and_lock(i);
  404.             if (irq) {
  405.                 /* The IRQ handler was found. */
  406.                 irq->handler(irq, irq->arg);
  407.                 spinlock_unlock(&irq->lock);
  408.             } else {
  409.                 /* Spurious interrupt.*/
  410.                 dprintf("cpu%d: spurious interrupt (inum=%d)\n",
  411.                     CPU->id, i);
  412.             }
  413.         }
  414.     }
  415. }
  416.  
  417. /** Returns address of framebuffer device.
  418.  *
  419.  *  @return Address of framebuffer device.
  420.  */
  421. uintptr_t qemu_icp_get_fb_address(void)
  422. {
  423.     if (!vga_init) {
  424.         icp_vga_init();
  425.         vga_init = true;
  426.     }
  427.     return (uintptr_t) QEMU_ICP_FB;
  428. }
  429.  
  430.  
  431. /** @}
  432.  */
  433.