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  1. /*
  2.  * Copyright (c) 2007 Michal Kebrt, Petr Stepan
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup arm32qemu_icp
  30.  * @{
  31.  */
  32. /** @file
  33.  *  @brief QEMU icp drivers.
  34.  */
  35.  
  36. #include <interrupt.h>
  37. #include <ipc/irq.h>
  38. #include <console/chardev.h>
  39. #include <arch/drivers/qemu.h>
  40. #include <console/console.h>
  41. #include <sysinfo/sysinfo.h>
  42. #include <print.h>
  43. #include <ddi/device.h>
  44. #include <mm/page.h>
  45. #include <arch/machine.h>
  46. #include <arch/debug/print.h>
  47.  
  48. /* Addresses of devices. */
  49. #define QEMU_ICP_VIDEORAM            0x16000000
  50. #define QEMU_ICP_KBD                 0x18000000
  51. #define QEMU_ICP_HALT_OFFSET         0x10
  52. #define QEMU_ICP_RTC                 0x13000000
  53. #define QEMU_ICP_RTC_FREQ_OFFSET     0x100
  54. #define QEMU_ICP_RTC_ACK_OFFSET      0x110
  55. #define QEMU_ICP_IRQC                0x14000000
  56. #define QEMU_ICP_IRQC_MASK_OFFSET    0x8
  57. #define QEMU_ICP_IRQC_UNMASK_OFFSET  0xC
  58. #define QEMU_ICP_MP                  0x11000000
  59. #define QEMU_ICP_MP_MEMSIZE_OFFSET   0x0090
  60. #define QEMU_ICP_FB                  0x94000
  61.  
  62. #define ICP_VGA              0xC0000000
  63. #define ICP_CMCR             0x10000000
  64.  
  65. /* IRQs */
  66. #define QEMU_ICP_KBD_IRQ        3
  67. #define QEMU_ICP_TIMER_IRQ  5
  68.  
  69. static qemu_icp_hw_map_t qemu_icp_hw_map;
  70. static chardev_t console;
  71. static irq_t qemu_icp_console_irq;
  72. static irq_t qemu_icp_timer_irq;
  73.  
  74. static bool hw_map_init_called = false;
  75. static bool vga_init = false;
  76.  
  77. static void qemu_icp_kbd_enable(chardev_t *dev);
  78. static void qemu_icp_kbd_disable(chardev_t *dev);
  79. static void qemu_icp_write(chardev_t *dev, const char ch);
  80. static char qemu_icp_do_read(chardev_t *dev);
  81. void icp_vga_init(void);
  82.  
  83. static chardev_operations_t qemu_icp_ops = {
  84.     .resume = qemu_icp_kbd_enable,
  85.     .suspend = qemu_icp_kbd_disable,
  86.     .write = qemu_icp_write,
  87.     .read = qemu_icp_do_read,
  88. };
  89.  
  90. /** Initializes the vga
  91.  *
  92.  */
  93. void icp_vga_init(void)
  94. {
  95.     *(uint32_t*)((char *)(qemu_icp_hw_map.cmcr)+0x14) = 0xA05F0000;
  96.     *(uint32_t*)((char *)(qemu_icp_hw_map.cmcr)+0x1C) = 0x12C11000;
  97.     *(uint32_t*)qemu_icp_hw_map.vga = 0x3F1F3F9C;
  98.     *(uint32_t*)((char *)(qemu_icp_hw_map.vga) + 0x4) = 0x080B61DF;
  99.     *(uint32_t*)((char *)(qemu_icp_hw_map.vga) + 0x8) = 0x067F3800;
  100.     *(uint32_t*)((char *)(qemu_icp_hw_map.vga) + 0x10) = QEMU_ICP_FB;
  101.     *(uint32_t *)((char *)(qemu_icp_hw_map.vga) + 0x1C) = 0x182B;
  102.     *(uint32_t*)((char *)(qemu_icp_hw_map.cmcr)+0xC) = 0x33805000;
  103.    
  104. }
  105.  
  106. /** Returns the mask of active interrupts. */
  107. static inline uint32_t qemu_icp_irqc_get_sources(void)
  108. {
  109.     return *((uint32_t *) qemu_icp_hw_map.irqc);
  110. }
  111.  
  112.  
  113. /** Masks interrupt.
  114.  *
  115.  * @param irq interrupt number
  116.  */
  117. static inline void qemu_icp_irqc_mask(uint32_t irq)
  118. {
  119.     *((uint32_t *) qemu_icp_hw_map.irqc_mask) = irq;
  120. }
  121.  
  122.  
  123. /** Unmasks interrupt.
  124.  *
  125.  * @param irq interrupt number
  126.  */
  127. static inline void qemu_icp_irqc_unmask(uint32_t irq)
  128. {
  129.     *((uint32_t *) qemu_icp_hw_map.irqc_unmask) = irq;
  130. }
  131.  
  132.  
  133. /** Initializes #qemu_icp_hw_map. */
  134. void qemu_icp_hw_map_init(void)
  135. {
  136.     qemu_icp_hw_map.videoram = hw_map(QEMU_ICP_VIDEORAM, PAGE_SIZE);
  137.     qemu_icp_hw_map.kbd = hw_map(QEMU_ICP_KBD, PAGE_SIZE);
  138.     qemu_icp_hw_map.rtc = hw_map(QEMU_ICP_RTC, PAGE_SIZE);
  139.     qemu_icp_hw_map.irqc = hw_map(QEMU_ICP_IRQC, PAGE_SIZE);
  140.  
  141.     qemu_icp_hw_map.rtc_freq = qemu_icp_hw_map.rtc + QEMU_ICP_RTC_FREQ_OFFSET;
  142.     qemu_icp_hw_map.rtc_ack = qemu_icp_hw_map.rtc + QEMU_ICP_RTC_ACK_OFFSET;
  143.     qemu_icp_hw_map.irqc_mask = qemu_icp_hw_map.irqc + QEMU_ICP_IRQC_MASK_OFFSET;
  144.     qemu_icp_hw_map.irqc_unmask = qemu_icp_hw_map.irqc +
  145.         QEMU_ICP_IRQC_UNMASK_OFFSET;
  146.     qemu_icp_hw_map.cmcr = hw_map(ICP_CMCR, PAGE_SIZE);
  147.     qemu_icp_hw_map.vga = hw_map(ICP_VGA, PAGE_SIZE);
  148.  
  149.     //icp_vga_init();
  150.  
  151.     hw_map_init_called = true;
  152. }
  153.  
  154.  
  155. /** Putchar that works with qemu_icp.
  156.  *
  157.  * @param dev Not used.
  158.  * @param ch Characted to be printed.
  159.  */
  160. static void qemu_icp_write(chardev_t *dev, const char ch)
  161. {
  162.     *((char *) qemu_icp_hw_map.videoram) = ch;
  163. }
  164.  
  165. /** Enables qemu_icp keyboard (interrupt unmasked).
  166.  *
  167.  * @param dev Not used.
  168.  *
  169.  * Called from getc().
  170.  */
  171. static void qemu_icp_kbd_enable(chardev_t *dev)
  172. {
  173.     qemu_icp_irqc_unmask(QEMU_ICP_KBD_IRQ);
  174. }
  175.  
  176. /** Disables qemu_icp keyboard (interrupt masked).
  177.  *
  178.  * @param dev not used
  179.  *
  180.  * Called from getc().
  181.  */
  182. static void qemu_icp_kbd_disable(chardev_t *dev)
  183. {
  184.     qemu_icp_irqc_mask(QEMU_ICP_KBD_IRQ);
  185. }
  186.  
  187. /** Read character using polling, assume interrupts disabled.
  188.  *
  189.  *  @param dev Not used.
  190.  */
  191. static char qemu_icp_do_read(chardev_t *dev)
  192. {
  193.     char ch;
  194.  
  195.     while (1) {
  196.         ch = *((volatile char *) qemu_icp_hw_map.kbd);
  197.         if (ch) {
  198.             if (ch == '\r')
  199.                 return '\n';
  200.             if (ch == 0x7f)
  201.                 return '\b';
  202.             return ch;
  203.         }
  204.     }
  205. }
  206.  
  207. /** Process keyboard interrupt.
  208.  *  
  209.  *  @param irq IRQ information.
  210.  *  @param arg Not used.
  211.  */
  212. static void qemu_icp_irq_handler(irq_t *irq, void *arg, ...)
  213. {
  214.     if ((irq->notif_cfg.notify) && (irq->notif_cfg.answerbox)) {
  215.         ipc_irq_send_notif(irq);
  216.     } else {
  217.         char ch = 0;
  218.        
  219.         ch = *((char *) qemu_icp_hw_map.kbd);
  220.         if (ch == '\r') {
  221.             ch = '\n';
  222.         }
  223.         if (ch == 0x7f) {
  224.             ch = '\b';
  225.         }
  226.         chardev_push_character(&console, ch);
  227.     }
  228. }
  229.  
  230. static irq_ownership_t qemu_icp_claim(void)
  231. {
  232.     return IRQ_ACCEPT;
  233. }
  234.  
  235.  
  236. /** Acquire console back for kernel. */
  237. void qemu_icp_grab_console(void)
  238. {
  239.     ipl_t ipl = interrupts_disable();
  240.     spinlock_lock(&qemu_icp_console_irq.lock);
  241.     qemu_icp_console_irq.notif_cfg.notify = false;
  242.     spinlock_unlock(&qemu_icp_console_irq.lock);
  243.     interrupts_restore(ipl);
  244. }
  245.  
  246. /** Return console to userspace. */
  247. void qemu_icp_release_console(void)
  248. {
  249.     ipl_t ipl = interrupts_disable();
  250.     spinlock_lock(&qemu_icp_console_irq.lock);
  251.     if (qemu_icp_console_irq.notif_cfg.answerbox) {
  252.         qemu_icp_console_irq.notif_cfg.notify = true;
  253.     }
  254.     spinlock_unlock(&qemu_icp_console_irq.lock);
  255.     interrupts_restore(ipl);
  256. }
  257.  
  258. /** Initializes console object representing qemu_icp console.
  259.  *
  260.  *  @param devno device number.
  261.  */
  262. void qemu_icp_console_init(devno_t devno)
  263. {
  264.     chardev_initialize("qemu_icp_console", &console, &qemu_icp_ops);
  265.     stdin = &console;
  266.     stdout = &console;
  267.    
  268.     irq_initialize(&qemu_icp_console_irq);
  269.     qemu_icp_console_irq.devno = devno;
  270.     qemu_icp_console_irq.inr = QEMU_ICP_KBD_IRQ;
  271.     qemu_icp_console_irq.claim = qemu_icp_claim;
  272.     qemu_icp_console_irq.handler = qemu_icp_irq_handler;
  273.     irq_register(&qemu_icp_console_irq);
  274.    
  275.     qemu_icp_irqc_unmask(QEMU_ICP_KBD_IRQ);
  276.    
  277.     sysinfo_set_item_val("kbd", NULL, true);
  278.     sysinfo_set_item_val("kbd.devno", NULL, devno);
  279.     sysinfo_set_item_val("kbd.inr", NULL, QEMU_ICP_KBD_IRQ);
  280.     sysinfo_set_item_val("kbd.address.virtual", NULL, qemu_icp_hw_map.kbd);
  281. }
  282.  
  283. /** Starts qemu_icp Real Time Clock device, which asserts regular interrupts.
  284.  *
  285.  * @param frequency Interrupts frequency (0 disables RTC).
  286.  */
  287. static void qemu_icp_timer_start(uint32_t frequency)
  288. {
  289.     *((uint32_t*) qemu_icp_hw_map.rtc_freq) = frequency;
  290. }
  291.  
  292. static irq_ownership_t qemu_icp_timer_claim(void)
  293. {
  294.     return IRQ_ACCEPT;
  295. }
  296.  
  297. /** Timer interrupt handler.
  298.  *
  299.  * @param irq Interrupt information.
  300.  * @param arg Not used.
  301.  */
  302. static void qemu_icp_timer_irq_handler(irq_t *irq, void *arg, ...)
  303. {
  304.     /*
  305.     * We are holding a lock which prevents preemption.
  306.     * Release the lock, call clock() and reacquire the lock again.
  307.     */
  308.     spinlock_unlock(&irq->lock);
  309.     clock();
  310.     spinlock_lock(&irq->lock);
  311.  
  312.     /* acknowledge tick */
  313.     *((uint32_t*) qemu_icp_hw_map.rtc_ack) = 0;
  314. }
  315.  
  316. /** Initializes and registers timer interrupt handler. */
  317. static void qemu_icp_timer_irq_init(void)
  318. {
  319.     irq_initialize(&qemu_icp_timer_irq);
  320.     qemu_icp_timer_irq.devno = device_assign_devno();
  321.     qemu_icp_timer_irq.inr = QEMU_ICP_TIMER_IRQ;
  322.     qemu_icp_timer_irq.claim = qemu_icp_timer_claim;
  323.     qemu_icp_timer_irq.handler = qemu_icp_timer_irq_handler;
  324.  
  325.     irq_register(&qemu_icp_timer_irq);
  326. }
  327.  
  328.  
  329. /** Starts timer.
  330.  *
  331.  * Initiates regular timer interrupts after initializing
  332.  * corresponding interrupt handler.
  333.  */
  334. void qemu_icp_timer_irq_start(void)
  335. {
  336.     qemu_icp_timer_irq_init();
  337.     qemu_icp_timer_start(QEMU_ICP_TIMER_FREQ);
  338. }
  339.  
  340. /** Returns the size of emulated memory.
  341.  *
  342.  * @return Size in bytes.
  343.  */
  344. size_t qemu_icp_get_memory_size(void)
  345. {
  346.     //return  *((int *) (QEMU_ICP_MP + QEMU_ICP_MP_MEMSIZE_OFFSET));
  347.     return 0x2000000;
  348. }
  349.  
  350. /** Prints a character.
  351.  *
  352.  *  @param ch Character to be printed.
  353.  */
  354. void qemu_icp_debug_putc(char ch)
  355. {
  356.     char *addr = 0;
  357.     if (!hw_map_init_called) {
  358.         addr = (char *) QEMU_ICP_KBD;
  359.     } else {
  360.         addr = (char *) qemu_icp_hw_map.videoram;
  361.     }
  362.    
  363.     if (ch == '\n')
  364.         *(addr) = '\r';
  365.     *(addr) = ch;
  366. }
  367.  
  368. /** Stops qemu_icp. */
  369. void qemu_icp_cpu_halt(void)
  370. {
  371.     char * addr = 0;
  372.     if (!hw_map_init_called) {
  373.         addr = (char *) QEMU_ICP_KBD;
  374.     } else {
  375.         addr = (char *) qemu_icp_hw_map.videoram;
  376.     }
  377.    
  378.     *(addr + QEMU_ICP_HALT_OFFSET) = '\0';
  379. }
  380.  
  381. /** Gxemul specific interrupt exception handler.
  382.  *
  383.  * Determines sources of the interrupt from interrupt controller and
  384.  * calls high-level handlers for them.
  385.  *
  386.  * @param exc_no Interrupt exception number.
  387.  * @param istate Saved processor state.
  388.  */
  389. void qemu_icp_irq_exception(int exc_no, istate_t *istate)
  390. {
  391.     uint32_t sources = qemu_icp_irqc_get_sources();
  392.     int i;
  393.    
  394.     for (i = 0; i < QEMU_ICP_IRQC_MAX_IRQ; i++) {
  395.         if (sources & (1 << i)) {
  396.             irq_t *irq = irq_dispatch_and_lock(i);
  397.             if (irq) {
  398.                 /* The IRQ handler was found. */
  399.                 irq->handler(irq, irq->arg);
  400.                 spinlock_unlock(&irq->lock);
  401.             } else {
  402.                 /* Spurious interrupt.*/
  403.                 dprintf("cpu%d: spurious interrupt (inum=%d)\n",
  404.                     CPU->id, i);
  405.             }
  406.         }
  407.     }
  408. }
  409.  
  410. /** Returns address of framebuffer device.
  411.  *
  412.  *  @return Address of framebuffer device.
  413.  */
  414. uintptr_t qemu_icp_get_fb_address(void)
  415. {
  416.     if (!vga_init) {
  417.         icp_vga_init();
  418.         vga_init = true;
  419.     }
  420.     return (uintptr_t) QEMU_ICP_FB;
  421. }
  422.  
  423.  
  424. /** @}
  425.  */
  426.