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  1. /*
  2.  * Copyright (C) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup sparc64mm  
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #include <arch/mm/tlb.h>
  36. #include <mm/tlb.h>
  37. #include <mm/as.h>
  38. #include <mm/asid.h>
  39. #include <arch/mm/frame.h>
  40. #include <arch/mm/page.h>
  41. #include <arch/mm/mmu.h>
  42. #include <arch/interrupt.h>
  43. #include <arch.h>
  44. #include <print.h>
  45. #include <arch/types.h>
  46. #include <typedefs.h>
  47. #include <config.h>
  48. #include <arch/trap/trap.h>
  49. #include <panic.h>
  50. #include <arch/asm.h>
  51. #include <symtab.h>
  52.  
  53. static void dtlb_pte_copy(pte_t *t);
  54. static void do_fast_data_access_mmu_miss_fault(istate_t *istate, const char *str);
  55.  
  56. char *context_encoding[] = {
  57.     "Primary",
  58.     "Secondary",
  59.     "Nucleus",
  60.     "Reserved"
  61. };
  62.  
  63. void tlb_arch_init(void)
  64. {
  65.     /*
  66.      * TLBs are actually initialized early
  67.      * in start.S.
  68.      */
  69. }
  70.  
  71. /** Insert privileged mapping into DMMU TLB.
  72.  *
  73.  * @param page Virtual page address.
  74.  * @param frame Physical frame address.
  75.  * @param pagesize Page size.
  76.  * @param locked True for permanent mappings, false otherwise.
  77.  * @param cacheable True if the mapping is cacheable, false otherwise.
  78.  */
  79. void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable)
  80. {
  81.     tlb_tag_access_reg_t tag;
  82.     tlb_data_t data;
  83.     page_address_t pg;
  84.     frame_address_t fr;
  85.  
  86.     pg.address = page;
  87.     fr.address = frame;
  88.  
  89.     tag.value = ASID_KERNEL;
  90.     tag.vpn = pg.vpn;
  91.  
  92.     dtlb_tag_access_write(tag.value);
  93.  
  94.     data.value = 0;
  95.     data.v = true;
  96.     data.size = pagesize;
  97.     data.pfn = fr.pfn;
  98.     data.l = locked;
  99.     data.cp = cacheable;
  100.     data.cv = cacheable;
  101.     data.p = true;
  102.     data.w = true;
  103.     data.g = true;
  104.  
  105.     dtlb_data_in_write(data.value);
  106. }
  107.  
  108. void dtlb_pte_copy(pte_t *t)
  109. {
  110. }
  111.  
  112. /** ITLB miss handler. */
  113. void fast_instruction_access_mmu_miss(int n, istate_t *istate)
  114. {
  115.     panic("%s\n", __FUNCTION__);
  116. }
  117.  
  118. /** DTLB miss handler.
  119.  *
  120.  * Note that some faults (e.g. kernel faults) were already resolved
  121.  * by the low-level, assembly language part of the fast_data_access_mmu_miss
  122.  * handler.
  123.  */
  124. void fast_data_access_mmu_miss(int n, istate_t *istate)
  125. {
  126.     tlb_tag_access_reg_t tag;
  127.     uintptr_t va;
  128.     pte_t *t;
  129.  
  130.     tag.value = dtlb_tag_access_read();
  131.     va = tag.vpn * PAGE_SIZE;
  132.     if (tag.context == ASID_KERNEL) {
  133.         if (!tag.vpn) {
  134.             /* NULL access in kernel */
  135.             do_fast_data_access_mmu_miss_fault(istate, __FUNCTION__);
  136.         }
  137.         do_fast_data_access_mmu_miss_fault(istate, "Unexpected kernel page fault.");
  138.     }
  139.  
  140.     page_table_lock(AS, true);
  141.     t = page_mapping_find(AS, va);
  142.     if (t) {
  143.         /*
  144.          * The mapping was found in the software page hash table.
  145.          * Insert it into DTLB.
  146.          */
  147.         dtlb_pte_copy(t);
  148.         page_table_unlock(AS, true);
  149.     } else {
  150.         /*
  151.          * Forward the page fault to the address space page fault handler.
  152.          */    
  153.         page_table_unlock(AS, true);
  154.         if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
  155.             do_fast_data_access_mmu_miss_fault(istate, __FUNCTION__);
  156.         }
  157.     }
  158. }
  159.  
  160. /** DTLB protection fault handler. */
  161. void fast_data_access_protection(int n, istate_t *istate)
  162. {
  163.     panic("%s\n", __FUNCTION__);
  164. }
  165.  
  166. /** Print contents of both TLBs. */
  167. void tlb_print(void)
  168. {
  169.     int i;
  170.     tlb_data_t d;
  171.     tlb_tag_read_reg_t t;
  172.    
  173.     printf("I-TLB contents:\n");
  174.     for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
  175.         d.value = itlb_data_access_read(i);
  176.         t.value = itlb_tag_read_read(i);
  177.        
  178.         printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
  179.             i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
  180.     }
  181.  
  182.     printf("D-TLB contents:\n");
  183.     for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
  184.         d.value = dtlb_data_access_read(i);
  185.         t.value = dtlb_tag_read_read(i);
  186.        
  187.         printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
  188.             i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
  189.     }
  190.  
  191. }
  192.  
  193. void do_fast_data_access_mmu_miss_fault(istate_t *istate, const char *str)
  194. {
  195.     tlb_tag_access_reg_t tag;
  196.     uintptr_t va;
  197.     char *tpc_str = get_symtab_entry(istate->tpc);
  198.  
  199.     tag.value = dtlb_tag_access_read();
  200.     va = tag.vpn * PAGE_SIZE;
  201.  
  202.     printf("Faulting page: %p, ASID=%d\n", va, tag.context);
  203.     printf("TPC=%p, (%s)\n", istate->tpc, tpc_str);
  204.     panic("%s\n", str);
  205. }
  206.  
  207. /** Invalidate all unlocked ITLB and DTLB entries. */
  208. void tlb_invalidate_all(void)
  209. {
  210.     int i;
  211.     tlb_data_t d;
  212.     tlb_tag_read_reg_t t;
  213.  
  214.     for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
  215.         d.value = itlb_data_access_read(i);
  216.         if (!d.l) {
  217.             t.value = itlb_tag_read_read(i);
  218.             d.v = false;
  219.             itlb_tag_access_write(t.value);
  220.             itlb_data_access_write(i, d.value);
  221.         }
  222.     }
  223.    
  224.     for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
  225.         d.value = dtlb_data_access_read(i);
  226.         if (!d.l) {
  227.             t.value = dtlb_tag_read_read(i);
  228.             d.v = false;
  229.             dtlb_tag_access_write(t.value);
  230.             dtlb_data_access_write(i, d.value);
  231.         }
  232.     }
  233.    
  234. }
  235.  
  236. /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
  237.  *
  238.  * @param asid Address Space ID.
  239.  */
  240. void tlb_invalidate_asid(asid_t asid)
  241. {
  242.     /* TODO: write asid to some Context register and encode the register in second parameter below. */
  243.     itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
  244.     dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
  245. }
  246.  
  247. /** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
  248.  *
  249.  * @param asid Address Space ID.
  250.  * @param page First page which to sweep out from ITLB and DTLB.
  251.  * @param cnt Number of ITLB and DTLB entries to invalidate.
  252.  */
  253. void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
  254. {
  255.     int i;
  256.    
  257.     for (i = 0; i < cnt; i++) {
  258.         /* TODO: write asid to some Context register and encode the register in second parameter below. */
  259.         itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
  260.         dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
  261.     }
  262. }
  263.  
  264. /** @}
  265.  */
  266.