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  1. /*
  2.  * Copyright (C) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup sparc64mm  
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #ifndef __sparc64_TLB_H__
  36. #define __sparc64_TLB_H__
  37.  
  38.  
  39. #define ITLB_ENTRY_COUNT        64
  40. #define DTLB_ENTRY_COUNT        64
  41.  
  42. #define MEM_CONTEXT_KERNEL      0
  43. #define MEM_CONTEXT_TEMP        1
  44.  
  45. /** Page sizes. */
  46. #define PAGESIZE_8K 0
  47. #define PAGESIZE_64K    1
  48. #define PAGESIZE_512K   2
  49. #define PAGESIZE_4M 3
  50.  
  51. /** Bit width of the TLB-locked portion of kernel address space. */
  52. #define KERNEL_PAGE_WIDTH       22  /* 4M */
  53.  
  54. /* TLB Demap Operation types. */
  55. #define TLB_DEMAP_PAGE      0
  56. #define TLB_DEMAP_CONTEXT   1
  57.  
  58. #define TLB_DEMAP_TYPE_SHIFT    6
  59.  
  60. /* TLB Demap Operation Context register encodings. */
  61. #define TLB_DEMAP_PRIMARY   0
  62. #define TLB_DEMAP_SECONDARY 1
  63. #define TLB_DEMAP_NUCLEUS   2
  64.  
  65. #define TLB_DEMAP_CONTEXT_SHIFT 4
  66.  
  67. /* TLB Tag Access shifts */
  68. #define TLB_TAG_ACCESS_CONTEXT_SHIFT    0
  69. #define TLB_TAG_ACCESS_VPN_SHIFT    13
  70.  
  71. #ifndef __ASM__
  72.  
  73. #include <arch/mm/tte.h>
  74. #include <arch/mm/mmu.h>
  75. #include <arch/mm/page.h>
  76. #include <arch/asm.h>
  77. #include <arch/barrier.h>
  78. #include <arch/types.h>
  79. #include <typedefs.h>
  80.  
  81. union tlb_context_reg {
  82.     uint64_t v;
  83.     struct {
  84.         unsigned long : 51;
  85.         unsigned context : 13;      /**< Context/ASID. */
  86.     } __attribute__ ((packed));
  87. };
  88. typedef union tlb_context_reg tlb_context_reg_t;
  89.  
  90. /** I-/D-TLB Data In/Access Register type. */
  91. typedef tte_data_t tlb_data_t;
  92.  
  93. /** I-/D-TLB Data Access Address in Alternate Space. */
  94. union tlb_data_access_addr {
  95.     uint64_t value;
  96.     struct {
  97.         uint64_t : 55;
  98.         unsigned tlb_entry : 6;
  99.         unsigned : 3;
  100.     } __attribute__ ((packed));
  101. };
  102. typedef union tlb_data_access_addr tlb_data_access_addr_t;
  103. typedef union tlb_data_access_addr tlb_tag_read_addr_t;
  104.  
  105. /** I-/D-TLB Tag Read Register. */
  106. union tlb_tag_read_reg {
  107.     uint64_t value;
  108.     struct {
  109.         uint64_t vpn : 51;      /**< Virtual Address bits 63:13. */
  110.         unsigned context : 13;  /**< Context identifier. */
  111.     } __attribute__ ((packed));
  112. };
  113. typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
  114. typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
  115.  
  116.  
  117. /** TLB Demap Operation Address. */
  118. union tlb_demap_addr {
  119.     uint64_t value;
  120.     struct {
  121.         uint64_t vpn: 51;       /**< Virtual Address bits 63:13. */
  122.         unsigned : 6;       /**< Ignored. */
  123.         unsigned type : 1;  /**< The type of demap operation. */
  124.         unsigned context : 2;   /**< Context register selection. */
  125.         unsigned : 4;       /**< Zero. */
  126.     } __attribute__ ((packed));
  127. };
  128. typedef union tlb_demap_addr tlb_demap_addr_t;
  129.  
  130. /** TLB Synchronous Fault Status Register. */
  131. union tlb_sfsr_reg {
  132.     uint64_t value;
  133.     struct {
  134.         unsigned long : 39; /**< Implementation dependent. */
  135.         unsigned nf : 1;    /**< Nonfaulting load. */
  136.         unsigned asi : 8;   /**< ASI. */
  137.         unsigned tm : 1;    /**< TLB miss. */
  138.         unsigned : 1;
  139.         unsigned ft : 7;    /**< Fault type. */
  140.         unsigned e : 1;     /**< Side-effect bit. */
  141.         unsigned ct : 2;    /**< Context Register selection. */
  142.         unsigned pr : 1;    /**< Privilege bit. */
  143.         unsigned w : 1;     /**< Write bit. */
  144.         unsigned ow : 1;    /**< Overwrite bit. */
  145.         unsigned fv : 1;    /**< Fault Valid bit. */
  146.     } __attribute__ ((packed));
  147. };
  148. typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
  149.  
  150. /** Read MMU Primary Context Register.
  151.  *
  152.  * @return Current value of Primary Context Register.
  153.  */
  154. static inline uint64_t mmu_primary_context_read(void)
  155. {
  156.     return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
  157. }
  158.  
  159. /** Write MMU Primary Context Register.
  160.  *
  161.  * @param v New value of Primary Context Register.
  162.  */
  163. static inline void mmu_primary_context_write(uint64_t v)
  164. {
  165.     asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
  166.     flush();
  167. }
  168.  
  169. /** Read MMU Secondary Context Register.
  170.  *
  171.  * @return Current value of Secondary Context Register.
  172.  */
  173. static inline uint64_t mmu_secondary_context_read(void)
  174. {
  175.     return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
  176. }
  177.  
  178. /** Write MMU Primary Context Register.
  179.  *
  180.  * @param v New value of Primary Context Register.
  181.  */
  182. static inline void mmu_secondary_context_write(uint64_t v)
  183. {
  184.     asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
  185.     flush();
  186. }
  187.  
  188. /** Read IMMU TLB Data Access Register.
  189.  *
  190.  * @param entry TLB Entry index.
  191.  *
  192.  * @return Current value of specified IMMU TLB Data Access Register.
  193.  */
  194. static inline uint64_t itlb_data_access_read(index_t entry)
  195. {
  196.     tlb_data_access_addr_t reg;
  197.    
  198.     reg.value = 0;
  199.     reg.tlb_entry = entry;
  200.     return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
  201. }
  202.  
  203. /** Write IMMU TLB Data Access Register.
  204.  *
  205.  * @param entry TLB Entry index.
  206.  * @param value Value to be written.
  207.  */
  208. static inline void itlb_data_access_write(index_t entry, uint64_t value)
  209. {
  210.     tlb_data_access_addr_t reg;
  211.    
  212.     reg.value = 0;
  213.     reg.tlb_entry = entry;
  214.     asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
  215.     flush();
  216. }
  217.  
  218. /** Read DMMU TLB Data Access Register.
  219.  *
  220.  * @param entry TLB Entry index.
  221.  *
  222.  * @return Current value of specified DMMU TLB Data Access Register.
  223.  */
  224. static inline uint64_t dtlb_data_access_read(index_t entry)
  225. {
  226.     tlb_data_access_addr_t reg;
  227.    
  228.     reg.value = 0;
  229.     reg.tlb_entry = entry;
  230.     return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
  231. }
  232.  
  233. /** Write DMMU TLB Data Access Register.
  234.  *
  235.  * @param entry TLB Entry index.
  236.  * @param value Value to be written.
  237.  */
  238. static inline void dtlb_data_access_write(index_t entry, uint64_t value)
  239. {
  240.     tlb_data_access_addr_t reg;
  241.    
  242.     reg.value = 0;
  243.     reg.tlb_entry = entry;
  244.     asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
  245.     membar();
  246. }
  247.  
  248. /** Read IMMU TLB Tag Read Register.
  249.  *
  250.  * @param entry TLB Entry index.
  251.  *
  252.  * @return Current value of specified IMMU TLB Tag Read Register.
  253.  */
  254. static inline uint64_t itlb_tag_read_read(index_t entry)
  255. {
  256.     tlb_tag_read_addr_t tag;
  257.  
  258.     tag.value = 0;
  259.     tag.tlb_entry = entry;
  260.     return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
  261. }
  262.  
  263. /** Read DMMU TLB Tag Read Register.
  264.  *
  265.  * @param entry TLB Entry index.
  266.  *
  267.  * @return Current value of specified DMMU TLB Tag Read Register.
  268.  */
  269. static inline uint64_t dtlb_tag_read_read(index_t entry)
  270. {
  271.     tlb_tag_read_addr_t tag;
  272.  
  273.     tag.value = 0;
  274.     tag.tlb_entry = entry;
  275.     return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
  276. }
  277.  
  278. /** Write IMMU TLB Tag Access Register.
  279.  *
  280.  * @param v Value to be written.
  281.  */
  282. static inline void itlb_tag_access_write(uint64_t v)
  283. {
  284.     asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
  285.     flush();
  286. }
  287.  
  288. /** Read IMMU TLB Tag Access Register.
  289.  *
  290.  * @return Current value of IMMU TLB Tag Access Register.
  291.  */
  292. static inline uint64_t itlb_tag_access_read(void)
  293. {
  294.     return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
  295. }
  296.  
  297. /** Write DMMU TLB Tag Access Register.
  298.  *
  299.  * @param v Value to be written.
  300.  */
  301. static inline void dtlb_tag_access_write(uint64_t v)
  302. {
  303.     asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
  304.     membar();
  305. }
  306.  
  307. /** Read DMMU TLB Tag Access Register.
  308.  *
  309.  * @return Current value of DMMU TLB Tag Access Register.
  310.  */
  311. static inline uint64_t dtlb_tag_access_read(void)
  312. {
  313.     return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
  314. }
  315.  
  316.  
  317. /** Write IMMU TLB Data in Register.
  318.  *
  319.  * @param v Value to be written.
  320.  */
  321. static inline void itlb_data_in_write(uint64_t v)
  322. {
  323.     asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
  324.     flush();
  325. }
  326.  
  327. /** Write DMMU TLB Data in Register.
  328.  *
  329.  * @param v Value to be written.
  330.  */
  331. static inline void dtlb_data_in_write(uint64_t v)
  332. {
  333.     asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
  334.     membar();
  335. }
  336.  
  337. /** Read ITLB Synchronous Fault Status Register.
  338.  *
  339.  * @return Current content of I-SFSR register.
  340.  */
  341. static inline uint64_t itlb_sfsr_read(void)
  342. {
  343.     return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
  344. }
  345.  
  346. /** Write ITLB Synchronous Fault Status Register.
  347.  *
  348.  * @param v New value of I-SFSR register.
  349.  */
  350. static inline void itlb_sfsr_write(uint64_t v)
  351. {
  352.     asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
  353.     flush();
  354. }
  355.  
  356. /** Read DTLB Synchronous Fault Status Register.
  357.  *
  358.  * @return Current content of D-SFSR register.
  359.  */
  360. static inline uint64_t dtlb_sfsr_read(void)
  361. {
  362.     return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
  363. }
  364.  
  365. /** Write DTLB Synchronous Fault Status Register.
  366.  *
  367.  * @param v New value of D-SFSR register.
  368.  */
  369. static inline void dtlb_sfsr_write(uint64_t v)
  370. {
  371.     asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
  372.     membar();
  373. }
  374.  
  375. /** Read DTLB Synchronous Fault Address Register.
  376.  *
  377.  * @return Current content of D-SFAR register.
  378.  */
  379. static inline uint64_t dtlb_sfar_read(void)
  380. {
  381.     return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
  382. }
  383.  
  384. /** Perform IMMU TLB Demap Operation.
  385.  *
  386.  * @param type Selects between context and page demap.
  387.  * @param context_encoding Specifies which Context register has Context ID for demap.
  388.  * @param page Address which is on the page to be demapped.
  389.  */
  390. static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
  391. {
  392.     tlb_demap_addr_t da;
  393.     page_address_t pg;
  394.    
  395.     da.value = 0;
  396.     pg.address = page;
  397.    
  398.     da.type = type;
  399.     da.context = context_encoding;
  400.     da.vpn = pg.vpn;
  401.    
  402.     asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the address within the ASI */
  403.     flush();
  404. }
  405.  
  406. /** Perform DMMU TLB Demap Operation.
  407.  *
  408.  * @param type Selects between context and page demap.
  409.  * @param context_encoding Specifies which Context register has Context ID for demap.
  410.  * @param page Address which is on the page to be demapped.
  411.  */
  412. static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
  413. {
  414.     tlb_demap_addr_t da;
  415.     page_address_t pg;
  416.    
  417.     da.value = 0;
  418.     pg.address = page;
  419.    
  420.     da.type = type;
  421.     da.context = context_encoding;
  422.     da.vpn = pg.vpn;
  423.    
  424.     asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the address within the ASI */
  425.     membar();
  426. }
  427.  
  428. extern void fast_instruction_access_mmu_miss(void);
  429. extern void fast_data_access_mmu_miss(void);
  430. extern void fast_data_access_protection(void);
  431.  
  432. extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable);
  433.  
  434. #endif /* !def __ASM__ */
  435.  
  436. #endif
  437.  
  438. /** @}
  439.  */
  440.