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  1. /*
  2.  * Copyright (C) 2005 Martin Decky
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /*
  30.  * PPC assembler macros
  31.  */
  32.  
  33. /* Condition Register Bit Fields */
  34. #define cr0 0
  35. #define cr1 1
  36. #define cr2 2
  37. #define cr3 3
  38. #define cr4 4
  39. #define cr5 5
  40. #define cr6 6
  41. #define cr7 7
  42.  
  43. /* General Purpose Registers (GPRs) */
  44. #define r0  0
  45. #define r1  1
  46. #define r2  2
  47. #define r3  3
  48. #define r4  4
  49. #define r5  5
  50. #define r6  6
  51. #define r7  7
  52. #define r8  8
  53. #define r9  9
  54. #define r10 10
  55. #define r11 11
  56. #define r12 12
  57. #define r13 13
  58. #define r14 14
  59. #define r15 15
  60. #define r16 16
  61. #define r17 17
  62. #define r18 18
  63. #define r19 19
  64. #define r20 20
  65. #define r21 21
  66. #define r22 22
  67. #define r23 23
  68. #define r24 24
  69. #define r25 25
  70. #define r26 26
  71. #define r27 27
  72. #define r28 28
  73. #define r29 29
  74. #define r30 30
  75. #define r31 31
  76.  
  77. /* GPR Aliases */
  78. #define sp  1
  79.  
  80. /* Floating Point Registers (FPRs) */
  81. #define fr0 0
  82. #define fr1 1
  83. #define fr2 2
  84. #define fr3 3
  85. #define fr4 4
  86. #define fr5 5
  87. #define fr6 6
  88. #define fr7 7
  89. #define fr8 8
  90. #define fr9 9
  91. #define fr10    10
  92. #define fr11    11
  93. #define fr12    12
  94. #define fr13    13
  95. #define fr14    14
  96. #define fr15    15
  97. #define fr16    16
  98. #define fr17    17
  99. #define fr18    18
  100. #define fr19    19
  101. #define fr20    20
  102. #define fr21    21
  103. #define fr22    22
  104. #define fr23    23
  105. #define fr24    24
  106. #define fr25    25
  107. #define fr26    26
  108. #define fr27    27
  109. #define fr28    28
  110. #define fr29    29
  111. #define fr30    30
  112. #define fr31    31
  113.  
  114. #define vr0 0
  115. #define vr1 1
  116. #define vr2 2
  117. #define vr3 3
  118. #define vr4 4
  119. #define vr5 5
  120. #define vr6 6
  121. #define vr7 7
  122. #define vr8 8
  123. #define vr9 9
  124. #define vr10    10
  125. #define vr11    11
  126. #define vr12    12
  127. #define vr13    13
  128. #define vr14    14
  129. #define vr15    15
  130. #define vr16    16
  131. #define vr17    17
  132. #define vr18    18
  133. #define vr19    19
  134. #define vr20    20
  135. #define vr21    21
  136. #define vr22    22
  137. #define vr23    23
  138. #define vr24    24
  139. #define vr25    25
  140. #define vr26    26
  141. #define vr27    27
  142. #define vr28    28
  143. #define vr29    29
  144. #define vr30    30
  145. #define vr31    31
  146.  
  147. #define evr0    0
  148. #define evr1    1
  149. #define evr2    2
  150. #define evr3    3
  151. #define evr4    4
  152. #define evr5    5
  153. #define evr6    6
  154. #define evr7    7
  155. #define evr8    8
  156. #define evr9    9
  157. #define evr10   10
  158. #define evr11   11
  159. #define evr12   12
  160. #define evr13   13
  161. #define evr14   14
  162. #define evr15   15
  163. #define evr16   16
  164. #define evr17   17
  165. #define evr18   18
  166. #define evr19   19
  167. #define evr20   20
  168. #define evr21   21
  169. #define evr22   22
  170. #define evr23   23
  171. #define evr24   24
  172. #define evr25   25
  173. #define evr26   26
  174. #define evr27   27
  175. #define evr28   28
  176. #define evr29   29
  177. #define evr30   30
  178. #define evr31   31
  179.  
  180. /* Special Purpose Registers (SPRs) */
  181. #define xer 1
  182. #define lr  8
  183. #define ctr 9
  184. #define dec 22
  185. #define srr0    26
  186. #define srr1    27
  187. #define sprg0   272
  188. #define sprg1   273
  189. #define sprg2   274
  190. #define sprg3   275
  191. #define prv 287
  192.  
  193. .macro REGISTERS_STORE r
  194.     stw r0, 0(\r)
  195.     stw r1, 4(\r)
  196.     stw r2, 8(\r)
  197.     stw r3, 12(\r)
  198.     stw r4, 16(\r)
  199.     stw r5, 20(\r)
  200.     stw r6, 24(\r)
  201.     stw r7, 28(\r)
  202.     stw r8, 32(\r)
  203.     stw r9, 36(\r)
  204.     stw r10, 40(\r)
  205.     stw r11, 44(\r)
  206.     stw r12, 48(\r)
  207.     stw r13, 52(\r)
  208.     stw r14, 56(\r)
  209.     stw r15, 60(\r)
  210.     stw r16, 64(\r)
  211.     stw r17, 68(\r)
  212.     stw r18, 72(\r)
  213.     stw r19, 76(\r)
  214.     stw r20, 80(\r)
  215.     stw r21, 84(\r)
  216.     stw r22, 88(\r)
  217.     stw r23, 92(\r)
  218.     stw r24, 96(\r)
  219.     stw r25, 100(\r)
  220.     stw r26, 104(\r)
  221.     stw r27, 108(\r)
  222.     stw r28, 112(\r)
  223.     stw r29, 116(\r)
  224.     stw r30, 120(\r)
  225.     stw r31, 124(\r)
  226. .endm
  227.  
  228. .macro REGISTERS_LOAD r
  229.     lwz r0, 0(\r)
  230.     lwz r1, 4(\r)
  231.     lwz r2, 8(\r)  
  232.     lwz r3, 12(\r)
  233.     lwz r4, 16(\r)
  234.     lwz r5, 20(\r)
  235.     lwz r6, 24(\r)
  236.     lwz r7, 28(\r)
  237.     lwz r8, 32(\r)
  238.     lwz r9, 36(\r)
  239.     lwz r10, 40(\r)
  240.     lwz r11, 44(\r)
  241.     lwz r12, 48(\r)
  242.     lwz r13, 52(\r)
  243.     lwz r14, 56(\r)
  244.     lwz r15, 60(\r)
  245.     lwz r16, 64(\r)
  246.     lwz r17, 68(\r)
  247.     lwz r18, 72(\r)
  248.     lwz r19, 76(\r)
  249.     lwz r20, 80(\r)
  250.     lwz r21, 84(\r)
  251.     lwz r22, 88(\r)
  252.     lwz r23, 92(\r)
  253.     lwz r24, 96(\r)
  254.     lwz r25, 100(\r)
  255.     lwz r26, 104(\r)
  256.     lwz r27, 108(\r)
  257.     lwz r28, 112(\r)
  258.     lwz r29, 116(\r)
  259.     lwz r30, 120(\r)
  260.     lwz r31, 124(\r)
  261. .endm
  262.