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  1. /*
  2.  * Copyright (C) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29.  /** @addtogroup ia64  
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #ifndef __ia64_REGISTER_H__
  36. #define __ia64_REGISTER_H__
  37.  
  38. #define CR_IVR_MASK 0xf
  39. #define PSR_IC_MASK 0x2000
  40. #define PSR_I_MASK  0x4000
  41. #define PSR_PK_MASK 0x8000
  42.  
  43. #define PSR_DT_MASK (1<<17)
  44. #define PSR_RT_MASK (1<<27)
  45.  
  46. #define PSR_DFL_MASK    (1<<18)
  47. #define PSR_DFH_MASK    (1<<19)
  48.  
  49. #define PSR_IT_MASK 0x0000001000000000
  50.  
  51. #define PSR_CPL_SHIFT       32
  52. #define PSR_CPL_MASK_SHIFTED    3
  53.  
  54. #define PFM_MASK        (~0x3fffffffff)
  55.  
  56. #define RSC_MODE_MASK   3
  57. #define RSC_PL_MASK 12
  58.  
  59. /** Application registers. */
  60. #define AR_KR0      0
  61. #define AR_KR1      1
  62. #define AR_KR2      2
  63. #define AR_KR3      3
  64. #define AR_KR4      4
  65. #define AR_KR5      5
  66. #define AR_KR6      6
  67. #define AR_KR7      7
  68. /* AR 8-15 reserved */
  69. #define AR_RSC      16
  70. #define AR_BSP      17
  71. #define AR_BSPSTORE 18
  72. #define AR_RNAT     19
  73. /* AR 20 reserved */
  74. #define AR_FCR      21
  75. /* AR 22-23 reserved */
  76. #define AR_EFLAG    24
  77. #define AR_CSD      25
  78. #define AR_SSD      26
  79. #define AR_CFLG     27
  80. #define AR_FSR      28
  81. #define AR_FIR      29
  82. #define AR_FDR      30
  83. /* AR 31 reserved */
  84. #define AR_CCV      32
  85. /* AR 33-35 reserved */
  86. #define AR_UNAT     36
  87. /* AR 37-39 reserved */
  88. #define AR_FPSR     40
  89. /* AR 41-43 reserved */
  90. #define AR_ITC      44
  91. /* AR 45-47 reserved */
  92. /* AR 48-63 ignored */
  93. #define AR_PFS      64
  94. #define AR_LC       65
  95. #define AR_EC       66
  96. /* AR 67-111 reserved */
  97. /* AR 112-127 ignored */
  98.  
  99. /** Control registers. */
  100. #define CR_DCR      0
  101. #define CR_ITM      1
  102. #define CR_IVA      2
  103. /* CR3-CR7 reserved */
  104. #define CR_PTA      8
  105. /* CR9-CR15 reserved */
  106. #define CR_IPSR     16
  107. #define CR_ISR      17
  108. /* CR18 reserved */
  109. #define CR_IIP      19
  110. #define CR_IFA      20
  111. #define CR_ITIR     21
  112. #define CR_IIPA     22
  113. #define CR_IFS      23
  114. #define CR_IIM      24
  115. #define CR_IHA      25
  116. /* CR26-CR63 reserved */
  117. #define CR_LID      64
  118. #define CR_IVR      65
  119. #define CR_TPR      66
  120. #define CR_EOI      67
  121. #define CR_IRR0     68
  122. #define CR_IRR1     69
  123. #define CR_IRR2     70
  124. #define CR_IRR3     71
  125. #define CR_ITV      72
  126. #define CR_PMV      73
  127. #define CR_CMCV     74
  128. /* CR75-CR79 reserved */
  129. #define CR_LRR0     80
  130. #define CR_LRR1     81
  131. /* CR82-CR127 reserved */
  132.  
  133. #ifndef __ASM__
  134.  
  135. #include <arch/types.h>
  136.  
  137. /** Processor Status Register. */
  138. union psr {
  139.     uint64_t value;
  140.     struct {
  141.         unsigned : 1;
  142.         unsigned be : 1;    /**< Big-Endian data accesses. */
  143.         unsigned up : 1;    /**< User Performance monitor enable. */
  144.         unsigned ac : 1;    /**< Alignment Check. */
  145.         unsigned mfl : 1;   /**< Lower floating-point register written. */
  146.         unsigned mfh : 1;   /**< Upper floating-point register written. */
  147.         unsigned : 7;
  148.         unsigned ic : 1;    /**< Interruption Collection. */
  149.         unsigned i : 1;     /**< Interrupt Bit. */
  150.         unsigned pk : 1;    /**< Protection Key enable. */
  151.         unsigned : 1;
  152.         unsigned dt : 1;    /**< Data address Translation. */
  153.         unsigned dfl : 1;   /**< Disabled Floating-point Low register set. */
  154.         unsigned dfh : 1;   /**< Disabled Floating-point High register set. */
  155.         unsigned sp : 1;    /**< Secure Performance monitors. */
  156.         unsigned pp : 1;    /**< Privileged Performance monitor enable. */
  157.         unsigned di : 1;    /**< Disable Instruction set transition. */
  158.         unsigned si : 1;    /**< Secure Interval timer. */
  159.         unsigned db : 1;    /**< Debug Breakpoint fault. */
  160.         unsigned lp : 1;    /**< Lower Privilege transfer trap. */
  161.         unsigned tb : 1;    /**< Taken Branch trap. */
  162.         unsigned rt : 1;    /**< Register Stack Translation. */
  163.         unsigned : 4;
  164.         unsigned cpl : 2;   /**< Current Privilege Level. */
  165.         unsigned is : 1;    /**< Instruction Set. */
  166.         unsigned mc : 1;    /**< Machine Check abort mask. */
  167.         unsigned it : 1;    /**< Instruction address Translation. */
  168.         unsigned id : 1;    /**< Instruction Debug fault disable. */
  169.         unsigned da : 1;    /**< Disable Data Access and Dirty-bit faults. */
  170.         unsigned dd : 1;    /**< Data Debug fault disable. */
  171.         unsigned ss : 1;    /**< Single Step enable. */
  172.         unsigned ri : 2;    /**< Restart Instruction. */
  173.         unsigned ed : 1;    /**< Exception Deferral. */
  174.         unsigned bn : 1;    /**< Register Bank. */
  175.         unsigned ia : 1;    /**< Disable Instruction Access-bit faults. */
  176.     } __attribute__ ((packed));
  177. };
  178. typedef union psr psr_t;
  179.  
  180. /** Register Stack Configuration Register */
  181. union rsc {
  182.     uint64_t value;
  183.     struct {
  184.         unsigned mode : 2;
  185.         unsigned pl : 2;    /**< Privilege Level. */
  186.         unsigned be : 1;    /**< Big-endian. */
  187.         unsigned : 11;
  188.         unsigned loadrs : 14;
  189.     } __attribute__ ((packed));
  190. };
  191. typedef union rsc rsc_t;
  192.  
  193. /** External Interrupt Vector Register */
  194. union cr_ivr {
  195.     uint8_t  vector;
  196.     uint64_t value;
  197. };
  198.  
  199. typedef union cr_ivr cr_ivr_t;
  200.  
  201. /** Task Priority Register */
  202. union cr_tpr {
  203.     struct {
  204.         unsigned : 4;
  205.         unsigned mic: 4;        /**< Mask Interrupt Class. */
  206.         unsigned : 8;
  207.         unsigned mmi: 1;        /**< Mask Maskable Interrupts. */
  208.     } __attribute__ ((packed));
  209.     uint64_t value;
  210. };
  211.  
  212. typedef union cr_tpr cr_tpr_t;
  213.  
  214. /** Interval Timer Vector */
  215. union cr_itv {
  216.     struct {
  217.         unsigned vector : 8;
  218.         unsigned : 4;
  219.         unsigned : 1;
  220.         unsigned : 3;
  221.         unsigned m : 1;         /**< Mask. */
  222.     } __attribute__ ((packed));
  223.     uint64_t value;
  224. };
  225.  
  226. typedef union cr_itv cr_itv_t;
  227.  
  228. /** Interruption Status Register */
  229. union cr_isr {
  230.     struct {
  231.         union {
  232.             /** General Exception code field structuring. */
  233.             struct {
  234.                 unsigned ge_na : 4;
  235.                 unsigned ge_code : 4;
  236.             } __attribute__ ((packed));
  237.             uint16_t code;
  238.         };
  239.         uint8_t vector;
  240.         unsigned : 8;
  241.         unsigned x : 1;         /**< Execute exception. */
  242.         unsigned w : 1;         /**< Write exception. */
  243.         unsigned r : 1;         /**< Read exception. */
  244.         unsigned na : 1;        /**< Non-access exception. */
  245.         unsigned sp : 1;        /**< Speculative load exception. */
  246.         unsigned rs : 1;        /**< Register stack. */
  247.         unsigned ir : 1;        /**< Incomplete Register frame. */
  248.         unsigned ni : 1;        /**< Nested Interruption. */
  249.         unsigned so : 1;        /**< IA-32 Supervisor Override. */
  250.         unsigned ei : 2;        /**< Excepting Instruction. */
  251.         unsigned ed : 1;        /**< Exception Deferral. */
  252.         unsigned : 20;
  253.     } __attribute__ ((packed));
  254.     uint64_t value;
  255. };
  256.  
  257. typedef union cr_isr cr_isr_t;
  258.  
  259. /** CPUID Register 3 */
  260. union cpuid3 {
  261.     struct {
  262.         uint8_t number;
  263.         uint8_t revision;
  264.         uint8_t model;
  265.         uint8_t family;
  266.         uint8_t archrev;
  267.     } __attribute__ ((packed));
  268.     uint64_t value;
  269. };
  270.  
  271. typedef union cpuid3 cpuid3_t;
  272.  
  273. #endif /* !__ASM__ */
  274.  
  275. #endif
  276.  
  277.  /** @}
  278.  */
  279.  
  280.