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  1. /*
  2.  * Copyright (c) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup ia64   
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #ifndef KERN_ia64_ASM_H_
  36. #define KERN_ia64_ASM_H_
  37.  
  38. #include <config.h>
  39. #include <arch/types.h>
  40. #include <arch/register.h>
  41.  
  42. #define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL
  43.  
  44. static inline void pio_write_8(ioport8_t *port, uint8_t v)
  45. {
  46.     uintptr_t prt = (uintptr_t) port;
  47.  
  48.     *((uint8_t *)(IA64_IOSPACE_ADDRESS +
  49.         ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
  50.  
  51.     asm volatile ("mf\n" ::: "memory");
  52. }
  53.  
  54. static inline void pio_write_16(ioport16_t *port, uint16_t v)
  55. {
  56.     uintptr_t prt = (uintptr_t) port;
  57.  
  58.     *((uint16_t *)(IA64_IOSPACE_ADDRESS +
  59.         ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
  60.  
  61.     asm volatile ("mf\n" ::: "memory");
  62. }
  63.  
  64. static inline void pio_write_32(ioport32_t *port, uint32_t v)
  65. {
  66.     uintptr_t prt = (uintptr_t) port;
  67.  
  68.     *((uint32_t *)(IA64_IOSPACE_ADDRESS +
  69.         ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
  70.  
  71.     asm volatile ("mf\n" ::: "memory");
  72. }
  73.  
  74. static inline uint8_t pio_read_8(ioport8_t *port)
  75. {
  76.     uintptr_t prt = (uintptr_t) port;
  77.  
  78.     asm volatile ("mf\n" ::: "memory");
  79.  
  80.     return *((uint8_t *)(IA64_IOSPACE_ADDRESS +
  81.         ((prt & 0xfff) | ((prt >> 2) << 12))));
  82. }
  83.  
  84. static inline uint16_t pio_read_16(ioport16_t *port)
  85. {
  86.     uintptr_t prt = (uintptr_t) port;
  87.  
  88.     asm volatile ("mf\n" ::: "memory");
  89.  
  90.     return *((uint16_t *)(IA64_IOSPACE_ADDRESS +
  91.         ((prt & 0xffE) | ((prt >> 2) << 12))));
  92. }
  93.  
  94. static inline uint32_t pio_read_32(ioport32_t *port)
  95. {
  96.     uintptr_t prt = (uintptr_t) port;
  97.  
  98.     asm volatile ("mf\n" ::: "memory");
  99.  
  100.     return *((uint32_t *)(IA64_IOSPACE_ADDRESS +
  101.         ((prt & 0xfff) | ((prt >> 2) << 12))));
  102. }
  103.  
  104. /** Return base address of current stack
  105.  *
  106.  * Return the base address of the current stack.
  107.  * The stack is assumed to be STACK_SIZE long.
  108.  * The stack must start on page boundary.
  109.  */
  110. static inline uintptr_t get_stack_base(void)
  111. {
  112.     uint64_t v;
  113.  
  114.     //I'm not sure why but this code bad inlines in scheduler,
  115.     //so THE shifts about 16B and causes kernel panic
  116.     //asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
  117.     //return v;
  118.    
  119.     //this code have the same meaning but inlines well
  120.     asm volatile ("mov %0 = r12" : "=r" (v)  );
  121.     return v & (~(STACK_SIZE-1));
  122. }
  123.  
  124. /** Return Processor State Register.
  125.  *
  126.  * @return PSR.
  127.  */
  128. static inline uint64_t psr_read(void)
  129. {
  130.     uint64_t v;
  131.    
  132.     asm volatile ("mov %0 = psr\n" : "=r" (v));
  133.    
  134.     return v;
  135. }
  136.  
  137. /** Read IVA (Interruption Vector Address).
  138.  *
  139.  * @return Return location of interruption vector table.
  140.  */
  141. static inline uint64_t iva_read(void)
  142. {
  143.     uint64_t v;
  144.    
  145.     asm volatile ("mov %0 = cr.iva\n" : "=r" (v));
  146.    
  147.     return v;
  148. }
  149.  
  150. /** Write IVA (Interruption Vector Address) register.
  151.  *
  152.  * @param v New location of interruption vector table.
  153.  */
  154. static inline void iva_write(uint64_t v)
  155. {
  156.     asm volatile ("mov cr.iva = %0\n" : : "r" (v));
  157. }
  158.  
  159.  
  160. /** Read IVR (External Interrupt Vector Register).
  161.  *
  162.  * @return Highest priority, pending, unmasked external interrupt vector.
  163.  */
  164. static inline uint64_t ivr_read(void)
  165. {
  166.     uint64_t v;
  167.    
  168.     asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));
  169.    
  170.     return v;
  171. }
  172.  
  173. static inline uint64_t cr64_read(void)
  174. {
  175.     uint64_t v;
  176.    
  177.     asm volatile ("mov %0 = cr64\n" : "=r" (v));
  178.    
  179.     return v;
  180. }
  181.  
  182.  
  183. /** Write ITC (Interval Timer Counter) register.
  184.  *
  185.  * @param v New counter value.
  186.  */
  187. static inline void itc_write(uint64_t v)
  188. {
  189.     asm volatile ("mov ar.itc = %0\n" : : "r" (v));
  190. }
  191.  
  192. /** Read ITC (Interval Timer Counter) register.
  193.  *
  194.  * @return Current counter value.
  195.  */
  196. static inline uint64_t itc_read(void)
  197. {
  198.     uint64_t v;
  199.    
  200.     asm volatile ("mov %0 = ar.itc\n" : "=r" (v));
  201.    
  202.     return v;
  203. }
  204.  
  205. /** Write ITM (Interval Timer Match) register.
  206.  *
  207.  * @param v New match value.
  208.  */
  209. static inline void itm_write(uint64_t v)
  210. {
  211.     asm volatile ("mov cr.itm = %0\n" : : "r" (v));
  212. }
  213.  
  214. /** Read ITM (Interval Timer Match) register.
  215.  *
  216.  * @return Match value.
  217.  */
  218. static inline uint64_t itm_read(void)
  219. {
  220.     uint64_t v;
  221.    
  222.     asm volatile ("mov %0 = cr.itm\n" : "=r" (v));
  223.    
  224.     return v;
  225. }
  226.  
  227. /** Read ITV (Interval Timer Vector) register.
  228.  *
  229.  * @return Current vector and mask bit.
  230.  */
  231. static inline uint64_t itv_read(void)
  232. {
  233.     uint64_t v;
  234.    
  235.     asm volatile ("mov %0 = cr.itv\n" : "=r" (v));
  236.    
  237.     return v;
  238. }
  239.  
  240. /** Write ITV (Interval Timer Vector) register.
  241.  *
  242.  * @param v New vector and mask bit.
  243.  */
  244. static inline void itv_write(uint64_t v)
  245. {
  246.     asm volatile ("mov cr.itv = %0\n" : : "r" (v));
  247. }
  248.  
  249. /** Write EOI (End Of Interrupt) register.
  250.  *
  251.  * @param v This value is ignored.
  252.  */
  253. static inline void eoi_write(uint64_t v)
  254. {
  255.     asm volatile ("mov cr.eoi = %0\n" : : "r" (v));
  256. }
  257.  
  258. /** Read TPR (Task Priority Register).
  259.  *
  260.  * @return Current value of TPR.
  261.  */
  262. static inline uint64_t tpr_read(void)
  263. {
  264.     uint64_t v;
  265.  
  266.     asm volatile ("mov %0 = cr.tpr\n"  : "=r" (v));
  267.    
  268.     return v;
  269. }
  270.  
  271. /** Write TPR (Task Priority Register).
  272.  *
  273.  * @param v New value of TPR.
  274.  */
  275. static inline void tpr_write(uint64_t v)
  276. {
  277.     asm volatile ("mov cr.tpr = %0\n" : : "r" (v));
  278. }
  279.  
  280. /** Disable interrupts.
  281.  *
  282.  * Disable interrupts and return previous
  283.  * value of PSR.
  284.  *
  285.  * @return Old interrupt priority level.
  286.  */
  287. static ipl_t interrupts_disable(void)
  288. {
  289.     uint64_t v;
  290.    
  291.     asm volatile (
  292.         "mov %0 = psr\n"
  293.         "rsm %1\n"
  294.         : "=r" (v)
  295.         : "i" (PSR_I_MASK)
  296.     );
  297.    
  298.     return (ipl_t) v;
  299. }
  300.  
  301. /** Enable interrupts.
  302.  *
  303.  * Enable interrupts and return previous
  304.  * value of PSR.
  305.  *
  306.  * @return Old interrupt priority level.
  307.  */
  308. static ipl_t interrupts_enable(void)
  309. {
  310.     uint64_t v;
  311.    
  312.     asm volatile (
  313.         "mov %0 = psr\n"
  314.         "ssm %1\n"
  315.         ";;\n"
  316.         "srlz.d\n"
  317.         : "=r" (v)
  318.         : "i" (PSR_I_MASK)
  319.     );
  320.    
  321.     return (ipl_t) v;
  322. }
  323.  
  324. /** Restore interrupt priority level.
  325.  *
  326.  * Restore PSR.
  327.  *
  328.  * @param ipl Saved interrupt priority level.
  329.  */
  330. static inline void interrupts_restore(ipl_t ipl)
  331. {
  332.     if (ipl & PSR_I_MASK)
  333.         (void) interrupts_enable();
  334.     else
  335.         (void) interrupts_disable();
  336. }
  337.  
  338. /** Return interrupt priority level.
  339.  *
  340.  * @return PSR.
  341.  */
  342. static inline ipl_t interrupts_read(void)
  343. {
  344.     return (ipl_t) psr_read();
  345. }
  346.  
  347. /** Disable protection key checking. */
  348. static inline void pk_disable(void)
  349. {
  350.     asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));
  351. }
  352.  
  353. extern void cpu_halt(void);
  354. extern void cpu_sleep(void);
  355. extern void asm_delay_loop(uint32_t t);
  356.  
  357. extern void switch_to_userspace(uintptr_t, uintptr_t, uintptr_t, uintptr_t,
  358.     uint64_t, uint64_t);
  359.  
  360. #endif
  361.  
  362. /** @}
  363.  */
  364.