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  1. /*
  2.  * Copyright (c) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup ia64   
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #ifndef KERN_ia64_ASM_H_
  36. #define KERN_ia64_ASM_H_
  37.  
  38. #include <config.h>
  39. #include <arch/types.h>
  40. #include <arch/register.h>
  41.  
  42.  
  43. #define IA64_IOSPACE_ADDRESS 0xE0000FFFFC000000ULL
  44.  
  45. static inline void  outb(uint64_t port,uint8_t v)
  46. {
  47.     *((char *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v;
  48.     asm volatile ("mf\n" ::: "memory");
  49. }
  50.  
  51.  
  52. static inline uint8_t inb(uint64_t port)
  53. {
  54.     asm volatile ("mf\n" ::: "memory");
  55.     return *((char *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 ))));
  56. }
  57.  
  58.  
  59.  
  60. /** Return base address of current stack
  61.  *
  62.  * Return the base address of the current stack.
  63.  * The stack is assumed to be STACK_SIZE long.
  64.  * The stack must start on page boundary.
  65.  */
  66. static inline uintptr_t get_stack_base(void)
  67. {
  68.     uint64_t v;
  69.  
  70.     asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
  71.    
  72.     return v;
  73. }
  74.  
  75. /** Return Processor State Register.
  76.  *
  77.  * @return PSR.
  78.  */
  79. static inline uint64_t psr_read(void)
  80. {
  81.     uint64_t v;
  82.    
  83.     asm volatile ("mov %0 = psr\n" : "=r" (v));
  84.    
  85.     return v;
  86. }
  87.  
  88. /** Read IVA (Interruption Vector Address).
  89.  *
  90.  * @return Return location of interruption vector table.
  91.  */
  92. static inline uint64_t iva_read(void)
  93. {
  94.     uint64_t v;
  95.    
  96.     asm volatile ("mov %0 = cr.iva\n" : "=r" (v));
  97.    
  98.     return v;
  99. }
  100.  
  101. /** Write IVA (Interruption Vector Address) register.
  102.  *
  103.  * @param v New location of interruption vector table.
  104.  */
  105. static inline void iva_write(uint64_t v)
  106. {
  107.     asm volatile ("mov cr.iva = %0\n" : : "r" (v));
  108. }
  109.  
  110.  
  111. /** Read IVR (External Interrupt Vector Register).
  112.  *
  113.  * @return Highest priority, pending, unmasked external interrupt vector.
  114.  */
  115. static inline uint64_t ivr_read(void)
  116. {
  117.     uint64_t v;
  118.    
  119.     asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));
  120.    
  121.     return v;
  122. }
  123.  
  124. /** Write ITC (Interval Timer Counter) register.
  125.  *
  126.  * @param v New counter value.
  127.  */
  128. static inline void itc_write(uint64_t v)
  129. {
  130.     asm volatile ("mov ar.itc = %0\n" : : "r" (v));
  131. }
  132.  
  133. /** Read ITC (Interval Timer Counter) register.
  134.  *
  135.  * @return Current counter value.
  136.  */
  137. static inline uint64_t itc_read(void)
  138. {
  139.     uint64_t v;
  140.    
  141.     asm volatile ("mov %0 = ar.itc\n" : "=r" (v));
  142.    
  143.     return v;
  144. }
  145.  
  146. /** Write ITM (Interval Timer Match) register.
  147.  *
  148.  * @param v New match value.
  149.  */
  150. static inline void itm_write(uint64_t v)
  151. {
  152.     asm volatile ("mov cr.itm = %0\n" : : "r" (v));
  153. }
  154.  
  155. /** Read ITM (Interval Timer Match) register.
  156.  *
  157.  * @return Match value.
  158.  */
  159. static inline uint64_t itm_read(void)
  160. {
  161.     uint64_t v;
  162.    
  163.     asm volatile ("mov %0 = cr.itm\n" : "=r" (v));
  164.    
  165.     return v;
  166. }
  167.  
  168. /** Read ITV (Interval Timer Vector) register.
  169.  *
  170.  * @return Current vector and mask bit.
  171.  */
  172. static inline uint64_t itv_read(void)
  173. {
  174.     uint64_t v;
  175.    
  176.     asm volatile ("mov %0 = cr.itv\n" : "=r" (v));
  177.    
  178.     return v;
  179. }
  180.  
  181. /** Write ITV (Interval Timer Vector) register.
  182.  *
  183.  * @param v New vector and mask bit.
  184.  */
  185. static inline void itv_write(uint64_t v)
  186. {
  187.     asm volatile ("mov cr.itv = %0\n" : : "r" (v));
  188. }
  189.  
  190. /** Write EOI (End Of Interrupt) register.
  191.  *
  192.  * @param v This value is ignored.
  193.  */
  194. static inline void eoi_write(uint64_t v)
  195. {
  196.     asm volatile ("mov cr.eoi = %0\n" : : "r" (v));
  197. }
  198.  
  199. /** Read TPR (Task Priority Register).
  200.  *
  201.  * @return Current value of TPR.
  202.  */
  203. static inline uint64_t tpr_read(void)
  204. {
  205.     uint64_t v;
  206.  
  207.     asm volatile ("mov %0 = cr.tpr\n"  : "=r" (v));
  208.    
  209.     return v;
  210. }
  211.  
  212. /** Write TPR (Task Priority Register).
  213.  *
  214.  * @param v New value of TPR.
  215.  */
  216. static inline void tpr_write(uint64_t v)
  217. {
  218.     asm volatile ("mov cr.tpr = %0\n" : : "r" (v));
  219. }
  220.  
  221. /** Disable interrupts.
  222.  *
  223.  * Disable interrupts and return previous
  224.  * value of PSR.
  225.  *
  226.  * @return Old interrupt priority level.
  227.  */
  228. static ipl_t interrupts_disable(void)
  229. {
  230.     uint64_t v;
  231.    
  232.     asm volatile (
  233.         "mov %0 = psr\n"
  234.         "rsm %1\n"
  235.         : "=r" (v)
  236.         : "i" (PSR_I_MASK)
  237.     );
  238.    
  239.     return (ipl_t) v;
  240. }
  241.  
  242. /** Enable interrupts.
  243.  *
  244.  * Enable interrupts and return previous
  245.  * value of PSR.
  246.  *
  247.  * @return Old interrupt priority level.
  248.  */
  249. static ipl_t interrupts_enable(void)
  250. {
  251.     uint64_t v;
  252.    
  253.     asm volatile (
  254.         "mov %0 = psr\n"
  255.         "ssm %1\n"
  256.         ";;\n"
  257.         "srlz.d\n"
  258.         : "=r" (v)
  259.         : "i" (PSR_I_MASK)
  260.     );
  261.    
  262.     return (ipl_t) v;
  263. }
  264.  
  265. /** Restore interrupt priority level.
  266.  *
  267.  * Restore PSR.
  268.  *
  269.  * @param ipl Saved interrupt priority level.
  270.  */
  271. static inline void interrupts_restore(ipl_t ipl)
  272. {
  273.     if (ipl & PSR_I_MASK)
  274.         (void) interrupts_enable();
  275.     else
  276.         (void) interrupts_disable();
  277. }
  278.  
  279. /** Return interrupt priority level.
  280.  *
  281.  * @return PSR.
  282.  */
  283. static inline ipl_t interrupts_read(void)
  284. {
  285.     return (ipl_t) psr_read();
  286. }
  287.  
  288. /** Disable protection key checking. */
  289. static inline void pk_disable(void)
  290. {
  291.     asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));
  292. }
  293.  
  294. extern void cpu_halt(void);
  295. extern void cpu_sleep(void);
  296. extern void asm_delay_loop(uint32_t t);
  297.  
  298. extern void switch_to_userspace(uintptr_t entry, uintptr_t sp, uintptr_t bsp, uintptr_t uspace_uarg, uint64_t ipsr, uint64_t rsc);
  299.  
  300. #endif
  301.  
  302. /** @}
  303.  */
  304.