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  1. /*
  2.  * Copyright (C) 2001-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #include <arch/types.h>
  30. #include <arch/smp/apic.h>
  31. #include <arch/smp/ap.h>
  32. #include <arch/smp/mp.h>
  33. #include <mm/page.h>
  34. #include <time/delay.h>
  35. #include <arch/interrupt.h>
  36. #include <print.h>
  37. #include <arch/asm.h>
  38. #include <arch.h>
  39.  
  40. #ifdef __SMP__
  41.  
  42. /*
  43.  * This is functional, far-from-general-enough interface to the APIC.
  44.  * Advanced Programmable Interrupt Controller for MP systems.
  45.  * Tested on:
  46.  *  Bochs 2.0.2 with 2-8 CPUs
  47.  *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
  48.  */
  49.  
  50. /*
  51.  * These variables either stay configured as initilalized, or are changed by
  52.  * the MP configuration code.
  53.  *
  54.  * Pay special attention to the volatile keyword. Without it, gcc -O2 would
  55.  * optimize the code too much and accesses to l_apic and io_apic, that must
  56.  * always be 32-bit, would use byte oriented instructions.
  57.  */
  58. volatile __u32 *l_apic = (__u32 *) 0xfee00000;
  59. volatile __u32 *io_apic = (__u32 *) 0xfec00000;
  60.  
  61. __u32 apic_id_mask = 0;
  62.  
  63. int apic_poll_errors(void);
  64.  
  65. void apic_init(void)
  66. {
  67.     __u32 tmp, id, i;
  68.  
  69.     trap_register(VECTOR_APIC_SPUR, apic_spurious);
  70.  
  71.     enable_irqs_function = io_apic_enable_irqs;
  72.     disable_irqs_function = io_apic_disable_irqs;
  73.     eoi_function = l_apic_eoi;
  74.    
  75.     /*
  76.      * Configure interrupt routing.
  77.      * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
  78.      * Other interrupts will be forwarded to the lowest priority CPU.
  79.      */
  80.     io_apic_disable_irqs(0xffff);
  81.     trap_register(VECTOR_CLK, l_apic_timer_interrupt);
  82.     for (i=1; i<16; i++) {
  83.         int pin;
  84.    
  85.         if ((pin = mp_irq_to_pin(i)) != -1)
  86.                 io_apic_change_ioredtbl(pin,0xf,IVT_IRQBASE+i,LOPRI);
  87.     }
  88.    
  89.  
  90.     /*
  91.      * Ensure that io_apic has unique ID.
  92.      */
  93.     tmp = io_apic_read(IOAPICID);
  94.     id = (tmp >> 24) & 0xf;
  95.     if ((1<<id) & apic_id_mask) {
  96.         int i;
  97.        
  98.         for (i=0; i<15; i++) {
  99.             if (!((1<<i) & apic_id_mask)) {
  100.                 io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) | (i<<24));
  101.                 break;
  102.             }
  103.         }
  104.     }
  105.  
  106.  
  107.  
  108.     /*
  109.      * Configure the BSP's lapic.
  110.      */
  111.     l_apic_init();
  112.     l_apic_debug();
  113. }
  114.  
  115. void apic_spurious(__u8 n, __u32 stack[])
  116. {
  117.     printf("cpu%d: APIC spurious interrupt\n", CPU->id);
  118. }
  119.  
  120. int apic_poll_errors(void)
  121. {
  122.     __u32 esr;
  123.    
  124.     esr = l_apic[ESR] & ~ESRClear;
  125.    
  126.     if ((esr>>0) & 1)
  127.         printf("Send CS Error\n");
  128.     if ((esr>>1) & 1)
  129.         printf("Receive CS Error\n");
  130.     if ((esr>>2) & 1)
  131.         printf("Send Accept Error\n");
  132.     if ((esr>>3) & 1)
  133.         printf("Receive Accept Error\n");
  134.     if ((esr>>5) & 1)
  135.         printf("Send Illegal Vector\n");
  136.     if ((esr>>6) & 1)
  137.         printf("Received Illegal Vector\n");
  138.     if ((esr>>7) & 1)
  139.         printf("Illegal Register Address\n");
  140.    
  141.     return !esr;
  142. }
  143.  
  144. /*
  145.  * Send all CPUs excluding CPU IPI vector.
  146.  */
  147. int l_apic_broadcast_custom_ipi(__u8 vector)
  148. {
  149.     __u32 lo;
  150.  
  151.     /*
  152.      * Read the ICR register in and zero all non-reserved fields.
  153.      */
  154.     lo = l_apic[ICRlo] & ICRloClear;
  155.  
  156.     lo |= DLVRMODE_FIXED | DESTMODE_LOGIC | LEVEL_ASSERT | SHORTHAND_EXCL | TRGRMODE_LEVEL | vector;
  157.    
  158.     l_apic[ICRlo] = lo;
  159.  
  160.     lo = l_apic[ICRlo] & ICRloClear;
  161.     if (lo & SEND_PENDING)
  162.         printf("IPI is pending.\n");
  163.  
  164.     return apic_poll_errors();
  165. }
  166.  
  167. /*
  168.  * Universal Start-up Algorithm for bringing up the AP processors.
  169.  */
  170. int l_apic_send_init_ipi(__u8 apicid)
  171. {
  172.     __u32 lo, hi;
  173.     int i;
  174.  
  175.     /*
  176.      * Read the ICR register in and zero all non-reserved fields.
  177.      */
  178.     lo = l_apic[ICRlo] & ICRloClear;
  179.     hi = l_apic[ICRhi] & ICRhiClear;
  180.    
  181.     lo |= DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
  182.     hi |= apicid << 24;
  183.    
  184.     l_apic[ICRhi] = hi;
  185.     l_apic[ICRlo] = lo;
  186.    
  187.     /*
  188.      * According to MP Specification, 20us should be enough to
  189.      * deliver the IPI.
  190.      */
  191.     delay(20);
  192.  
  193.     if (!apic_poll_errors()) return 0;
  194.  
  195.     lo = l_apic[ICRlo] & ICRloClear;
  196.     if (lo & SEND_PENDING)
  197.         printf("IPI is pending.\n");
  198.    
  199.     l_apic[ICRlo] = lo | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
  200.  
  201.     /*
  202.      * Wait 10ms as MP Specification specifies.
  203.      */
  204.     delay(10000);
  205.  
  206.     /*
  207.      * MP specification says this should not be done for 82489DX-based
  208.      * l_apic's. However, everything is ok as long as STARTUP IPI is ignored
  209.      * by 8249DX.
  210.      */
  211.     for (i = 0; i < 2; i++) {
  212.         lo = l_apic[ICRlo] & ICRloClear;
  213.         lo |= ((__address) ap_boot) / 4096; /* calculate the reset vector */
  214.         l_apic[ICRlo] = lo | DLVRMODE_STUP | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST |  TRGRMODE_LEVEL;
  215.         delay(200);
  216.     }
  217.    
  218.     return apic_poll_errors();
  219. }
  220.  
  221. void l_apic_init(void)
  222. {
  223.     __u32 tmp, t1, t2;
  224.     int cpu_id = config.cpu_active - 1;
  225.    
  226.  
  227.     /*
  228.      * Here we set local APIC ID's so that they match operating system's CPU ID's
  229.      * This operation is dangerous as it is model specific.
  230.      * TODO: some care should be taken.
  231.      * NOTE: CPU may not be used to define APIC ID
  232.      */
  233.     if (l_apic_id() != cpu_id) {
  234.         l_apic[L_APIC_ID] &= L_APIC_IDClear;
  235.         l_apic[L_APIC_ID] |= (l_apic[L_APIC_ID]&L_APIC_IDClear)|((cpu_id)<<L_APIC_IDShift);
  236.     }
  237.  
  238.     l_apic[LVT_Err] |= (1<<16);
  239.     l_apic[LVT_LINT0] |= (1<<16);
  240.     l_apic[LVT_LINT1] |= (1<<16);
  241.  
  242.     tmp = l_apic[SVR] & SVRClear;
  243.     l_apic[SVR] = tmp | (1<<8) | (VECTOR_APIC_SPUR);
  244.  
  245.     l_apic[TPR] &= TPRClear;
  246.  
  247.     if (CPU->arch.family >= 6)
  248.         enable_l_apic_in_msr();
  249.    
  250.     tmp = l_apic[ICRlo] & ICRloClear;
  251.     l_apic[ICRlo] = tmp | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_INCL | TRGRMODE_LEVEL;
  252.    
  253.     /*
  254.      * Program the timer for periodic mode and respective vector.
  255.      */
  256.  
  257.     l_apic[TDCR] &= TDCRClear;
  258.     l_apic[TDCR] |= 0xb;
  259.     tmp = l_apic[LVT_Tm] | (1<<17) | (VECTOR_CLK);
  260.     l_apic[LVT_Tm] = tmp & ~(1<<16);
  261.  
  262.     t1 = l_apic[CCRT];
  263.     l_apic[ICRT] = 0xffffffff;
  264.  
  265.     while (l_apic[CCRT] == t1)
  266.         ;
  267.        
  268.     t1 = l_apic[CCRT];
  269.     delay(1000);
  270.     t2 = l_apic[CCRT];
  271.    
  272.     l_apic[ICRT] = t1-t2;
  273. }
  274.  
  275. void l_apic_eoi(void)
  276. {
  277.     l_apic[EOI] = 0;
  278. }
  279.  
  280. void l_apic_debug(void)
  281. {
  282. #ifdef LAPIC_VERBOSE
  283.     int i, lint;
  284.  
  285.     printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
  286.  
  287.     printf("LVT_Tm: ");
  288.     if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(',');   
  289.     if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
  290.     if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
  291.     printf("%B\n", l_apic[LVT_Tm] & 0xff);
  292.    
  293.     for (i=0; i<2; i++) {
  294.         lint = i ? LVT_LINT1 : LVT_LINT0;
  295.         printf("LVT_LINT%d: ", i);
  296.         if (l_apic[lint] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
  297.         if (l_apic[lint] & (1<<15)) printf("level"); else printf("edge"); putchar(',');
  298.         printf("%d", l_apic[lint] & (1<<14)); putchar(',');
  299.         printf("%d", l_apic[lint] & (1<<13)); putchar(',');
  300.         if (l_apic[lint] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
  301.    
  302.         switch ((l_apic[lint]>>8)&7) {
  303.             case 0: printf("fixed"); break;
  304.             case 4: printf("NMI"); break;
  305.             case 7: printf("ExtINT"); break;
  306.         }
  307.         putchar(',');
  308.         printf("%B\n", l_apic[lint] & 0xff);   
  309.     }
  310.  
  311.     printf("LVT_Err: ");
  312.     if (l_apic[LVT_Err] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
  313.     if (l_apic[LVT_Err] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
  314.     printf("%B\n", l_apic[LVT_Err] & 0xff);
  315.  
  316.     /*
  317.      * This register is supported only on P6 and higher.
  318.      */
  319.     if (CPU->arch.family > 5) {
  320.         printf("LVT_PCINT: ");
  321.         if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
  322.         if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
  323.         switch ((l_apic[LVT_PCINT] >> 8)&7) {
  324.             case 0: printf("fixed"); break;
  325.             case 4: printf("NMI"); break;
  326.             case 7: printf("ExtINT"); break;
  327.         }
  328.         putchar(',');
  329.         printf("%B\n", l_apic[LVT_PCINT] & 0xff);
  330.     }
  331. #endif
  332. }
  333.  
  334. void l_apic_timer_interrupt(__u8 n, __u32 stack[])
  335. {
  336.     l_apic_eoi();
  337.     clock();
  338. }
  339.  
  340. inline __u8 l_apic_id(void)
  341. {
  342.     return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask;
  343. }
  344.  
  345. __u32 io_apic_read(__u8 address)
  346. {
  347.     __u32 tmp;
  348.    
  349.     tmp = io_apic[IOREGSEL] & ~0xf;
  350.     io_apic[IOREGSEL] = tmp | address;
  351.     return io_apic[IOWIN];
  352. }
  353.  
  354. void io_apic_write(__u8 address, __u32 x)
  355. {
  356.     __u32 tmp;
  357.  
  358.     tmp = io_apic[IOREGSEL] & ~0xf;
  359.     io_apic[IOREGSEL] = tmp | address;
  360.     io_apic[IOWIN] = x;
  361. }
  362.  
  363. void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags)
  364. {
  365.     __u32 reglo, reghi;
  366.     int dlvr = 0;
  367.    
  368.     if (flags & LOPRI)
  369.         dlvr = 1;
  370.    
  371.     reglo = io_apic_read(IOREDTBL + signal*2);
  372.     reghi = io_apic_read(IOREDTBL + signal*2 + 1);
  373.    
  374.     reghi &= ~0x0f000000;
  375.     reghi |= (dest<<24);
  376.  
  377.     reglo &= (~0x1ffff) | (1<<16); /* don't touch the mask */
  378.     reglo |= (0<<15) | (0<<13) | (0<<11) | (dlvr<<8) | v;
  379.  
  380.     io_apic_write(IOREDTBL + signal*2, reglo);     
  381.     io_apic_write(IOREDTBL + signal*2 + 1, reghi);
  382. }
  383.  
  384. void io_apic_disable_irqs(__u16 irqmask)
  385. {
  386.     int i,pin;
  387.     __u32 reglo;
  388.    
  389.     for (i=0;i<16;i++) {
  390.         if ((irqmask>>i) & 1) {
  391.             /*
  392.              * Mask the signal input in IO APIC if there is a
  393.              * mapping for the respective IRQ number.
  394.              */
  395.             pin = mp_irq_to_pin(i);
  396.             if (pin != -1) {
  397.                 reglo = io_apic_read(IOREDTBL + pin*2);
  398.                 reglo |= (1<<16);
  399.                 io_apic_write(IOREDTBL + pin*2,reglo);
  400.             }
  401.            
  402.         }
  403.     }
  404. }
  405.  
  406. void io_apic_enable_irqs(__u16 irqmask)
  407. {
  408.     int i,pin;
  409.     __u32 reglo;
  410.    
  411.     for (i=0;i<16;i++) {
  412.         if ((irqmask>>i) & 1) {
  413.             /*
  414.              * Unmask the signal input in IO APIC if there is a
  415.              * mapping for the respective IRQ number.
  416.              */
  417.             pin = mp_irq_to_pin(i);
  418.             if (pin != -1) {
  419.                 reglo = io_apic_read(IOREDTBL + pin*2);
  420.                 reglo &= ~(1<<16);
  421.                 io_apic_write(IOREDTBL + pin*2,reglo);
  422.             }
  423.            
  424.         }
  425.     }
  426.  
  427. }
  428.  
  429. #endif /* __SMP__ */
  430.