Subversion Repositories HelenOS

Rev

Rev 2071 | Rev 2218 | Go to most recent revision | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed

  1. /*
  2.  * Copyright (c) 2001-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup ia32   
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #include <arch/types.h>
  36. #include <arch/smp/apic.h>
  37. #include <arch/smp/ap.h>
  38. #include <arch/smp/mps.h>
  39. #include <arch/boot/boot.h>
  40. #include <mm/page.h>
  41. #include <time/delay.h>
  42. #include <interrupt.h>
  43. #include <arch/interrupt.h>
  44. #include <print.h>
  45. #include <arch/asm.h>
  46. #include <arch.h>
  47. #include <ddi/irq.h>
  48. #include <ddi/device.h>
  49.  
  50. #ifdef CONFIG_SMP
  51.  
  52. /*
  53.  * Advanced Programmable Interrupt Controller for SMP systems.
  54.  * Tested on:
  55.  *  Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
  56.  *  Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
  57.  *  VMware Workstation 5.5 with 2 CPUs
  58.  *  QEMU 0.8.0 with 2-15 CPUs
  59.  *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
  60.  *  ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
  61.  *  MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
  62.  */
  63.  
  64. /*
  65.  * These variables either stay configured as initilalized, or are changed by
  66.  * the MP configuration code.
  67.  *
  68.  * Pay special attention to the volatile keyword. Without it, gcc -O2 would
  69.  * optimize the code too much and accesses to l_apic and io_apic, that must
  70.  * always be 32-bit, would use byte oriented instructions.
  71.  */
  72. volatile uint32_t *l_apic = (uint32_t *) 0xfee00000;
  73. volatile uint32_t *io_apic = (uint32_t *) 0xfec00000;
  74.  
  75. uint32_t apic_id_mask = 0;
  76. static irq_t l_apic_timer_irq;
  77.  
  78. static int apic_poll_errors(void);
  79.  
  80. #ifdef LAPIC_VERBOSE
  81. static char *delmod_str[] = {
  82.     "Fixed",
  83.     "Lowest Priority",
  84.     "SMI",
  85.     "Reserved",
  86.     "NMI",
  87.     "INIT",
  88.     "STARTUP",
  89.     "ExtInt"
  90. };
  91.  
  92. static char *destmod_str[] = {
  93.     "Physical",
  94.     "Logical"
  95. };
  96.  
  97. static char *trigmod_str[] = {
  98.     "Edge",
  99.     "Level"
  100. };
  101.  
  102. static char *mask_str[] = {
  103.     "Unmasked",
  104.     "Masked"
  105. };
  106.  
  107. static char *delivs_str[] = {
  108.     "Idle",
  109.     "Send Pending"
  110. };
  111.  
  112. static char *tm_mode_str[] = {
  113.     "One-shot",
  114.     "Periodic"
  115. };
  116.  
  117. static char *intpol_str[] = {
  118.     "Polarity High",
  119.     "Polarity Low"
  120. };
  121. #endif /* LAPIC_VERBOSE */
  122.  
  123. /** APIC spurious interrupt handler.
  124.  *
  125.  * @param n Interrupt vector.
  126.  * @param istate Interrupted state.
  127.  */
  128. static void apic_spurious(int n, istate_t *istate)
  129. {
  130. #ifdef CONFIG_DEBUG
  131.     printf("cpu%d: APIC spurious interrupt\n", CPU->id);
  132. #endif
  133. }
  134.  
  135. static irq_ownership_t l_apic_timer_claim(void)
  136. {
  137.     return IRQ_ACCEPT;
  138. }
  139.  
  140. static void l_apic_timer_irq_handler(irq_t *irq, void *arg, ...)
  141. {
  142.     clock();
  143. }
  144.  
  145. /** Initialize APIC on BSP. */
  146. void apic_init(void)
  147. {
  148.     io_apic_id_t idreg;
  149.     unsigned int i;
  150.  
  151.     exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious);
  152.  
  153.     enable_irqs_function = io_apic_enable_irqs;
  154.     disable_irqs_function = io_apic_disable_irqs;
  155.     eoi_function = l_apic_eoi;
  156.    
  157.     /*
  158.      * Configure interrupt routing.
  159.      * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
  160.      * Other interrupts will be forwarded to the lowest priority CPU.
  161.      */
  162.     io_apic_disable_irqs(0xffff);
  163.    
  164.     irq_initialize(&l_apic_timer_irq);
  165.     l_apic_timer_irq.devno = device_assign_devno();
  166.     l_apic_timer_irq.inr = IRQ_CLK;
  167.     l_apic_timer_irq.claim = l_apic_timer_claim;
  168.     l_apic_timer_irq.handler = l_apic_timer_irq_handler;
  169.     irq_register(&l_apic_timer_irq);
  170.    
  171.     for (i = 0; i < IRQ_COUNT; i++) {
  172.         int pin;
  173.    
  174.         if ((pin = smp_irq_to_pin(i)) != -1)
  175.             io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE + i, LOPRI);
  176.     }
  177.    
  178.     /*
  179.      * Ensure that io_apic has unique ID.
  180.      */
  181.     idreg.value = io_apic_read(IOAPICID);
  182.     if ((1 << idreg.apic_id) & apic_id_mask) {  /* see if IO APIC ID is used already */
  183.         for (i = 0; i < APIC_ID_COUNT; i++) {
  184.             if (!((1 << i) & apic_id_mask)) {
  185.                 idreg.apic_id = i;
  186.                 io_apic_write(IOAPICID, idreg.value);
  187.                 break;
  188.             }
  189.         }
  190.     }
  191.  
  192.     /*
  193.      * Configure the BSP's lapic.
  194.      */
  195.     l_apic_init();
  196.  
  197.     l_apic_debug();
  198. }
  199.  
  200. /** Poll for APIC errors.
  201.  *
  202.  * Examine Error Status Register and report all errors found.
  203.  *
  204.  * @return 0 on error, 1 on success.
  205.  */
  206. int apic_poll_errors(void)
  207. {
  208.     esr_t esr;
  209.    
  210.     esr.value = l_apic[ESR];
  211.    
  212.     if (esr.send_checksum_error)
  213.         printf("Send Checksum Error\n");
  214.     if (esr.receive_checksum_error)
  215.         printf("Receive Checksum Error\n");
  216.     if (esr.send_accept_error)
  217.         printf("Send Accept Error\n");
  218.     if (esr.receive_accept_error)
  219.         printf("Receive Accept Error\n");
  220.     if (esr.send_illegal_vector)
  221.         printf("Send Illegal Vector\n");
  222.     if (esr.received_illegal_vector)
  223.         printf("Received Illegal Vector\n");
  224.     if (esr.illegal_register_address)
  225.         printf("Illegal Register Address\n");
  226.  
  227.     return !esr.err_bitmap;
  228. }
  229.  
  230. /** Send all CPUs excluding CPU IPI vector.
  231.  *
  232.  * @param vector Interrupt vector to be sent.
  233.  *
  234.  * @return 0 on failure, 1 on success.
  235.  */
  236. int l_apic_broadcast_custom_ipi(uint8_t vector)
  237. {
  238.     icr_t icr;
  239.  
  240.     icr.lo = l_apic[ICRlo];
  241.     icr.delmod = DELMOD_FIXED;
  242.     icr.destmod = DESTMOD_LOGIC;
  243.     icr.level = LEVEL_ASSERT;
  244.     icr.shorthand = SHORTHAND_ALL_EXCL;
  245.     icr.trigger_mode = TRIGMOD_LEVEL;
  246.     icr.vector = vector;
  247.  
  248.     l_apic[ICRlo] = icr.lo;
  249.  
  250.     icr.lo = l_apic[ICRlo];
  251.     if (icr.delivs == DELIVS_PENDING) {
  252. #ifdef CONFIG_DEBUG
  253.         printf("IPI is pending.\n");
  254. #endif
  255.     }
  256.  
  257.     return apic_poll_errors();
  258. }
  259.  
  260. /** Universal Start-up Algorithm for bringing up the AP processors.
  261.  *
  262.  * @param apicid APIC ID of the processor to be brought up.
  263.  *
  264.  * @return 0 on failure, 1 on success.
  265.  */
  266. int l_apic_send_init_ipi(uint8_t apicid)
  267. {
  268.     icr_t icr;
  269.     int i;
  270.  
  271.     /*
  272.      * Read the ICR register in and zero all non-reserved fields.
  273.      */
  274.     icr.lo = l_apic[ICRlo];
  275.     icr.hi = l_apic[ICRhi];
  276.    
  277.     icr.delmod = DELMOD_INIT;
  278.     icr.destmod = DESTMOD_PHYS;
  279.     icr.level = LEVEL_ASSERT;
  280.     icr.trigger_mode = TRIGMOD_LEVEL;
  281.     icr.shorthand = SHORTHAND_NONE;
  282.     icr.vector = 0;
  283.     icr.dest = apicid;
  284.    
  285.     l_apic[ICRhi] = icr.hi;
  286.     l_apic[ICRlo] = icr.lo;
  287.  
  288.     /*
  289.      * According to MP Specification, 20us should be enough to
  290.      * deliver the IPI.
  291.      */
  292.     delay(20);
  293.  
  294.     if (!apic_poll_errors())
  295.         return 0;
  296.  
  297.     icr.lo = l_apic[ICRlo];
  298.     if (icr.delivs == DELIVS_PENDING) {
  299. #ifdef CONFIG_DEBUG
  300.         printf("IPI is pending.\n");
  301. #endif
  302.     }
  303.  
  304.     icr.delmod = DELMOD_INIT;
  305.     icr.destmod = DESTMOD_PHYS;
  306.     icr.level = LEVEL_DEASSERT;
  307.     icr.shorthand = SHORTHAND_NONE;
  308.     icr.trigger_mode = TRIGMOD_LEVEL;
  309.     icr.vector = 0;
  310.     l_apic[ICRlo] = icr.lo;
  311.  
  312.     /*
  313.      * Wait 10ms as MP Specification specifies.
  314.      */
  315.     delay(10000);
  316.  
  317.     if (!is_82489DX_apic(l_apic[LAVR])) {
  318.         /*
  319.          * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
  320.          */
  321.         for (i = 0; i<2; i++) {
  322.             icr.lo = l_apic[ICRlo];
  323.             icr.vector = ((uintptr_t) ap_boot) / 4096; /* calculate the reset vector */
  324.             icr.delmod = DELMOD_STARTUP;
  325.             icr.destmod = DESTMOD_PHYS;
  326.             icr.level = LEVEL_ASSERT;
  327.             icr.shorthand = SHORTHAND_NONE;
  328.             icr.trigger_mode = TRIGMOD_LEVEL;
  329.             l_apic[ICRlo] = icr.lo;
  330.             delay(200);
  331.         }
  332.     }
  333.    
  334.     return apic_poll_errors();
  335. }
  336.  
  337. /** Initialize Local APIC. */
  338. void l_apic_init(void)
  339. {
  340.     lvt_error_t error;
  341.     lvt_lint_t lint;
  342.     tpr_t tpr;
  343.     svr_t svr;
  344.     icr_t icr;
  345.     tdcr_t tdcr;
  346.     lvt_tm_t tm;
  347.     ldr_t ldr;
  348.     dfr_t dfr;
  349.     uint32_t t1, t2;
  350.  
  351.     /* Initialize LVT Error register. */
  352.     error.value = l_apic[LVT_Err];
  353.     error.masked = true;
  354.     l_apic[LVT_Err] = error.value;
  355.  
  356.     /* Initialize LVT LINT0 register. */
  357.     lint.value = l_apic[LVT_LINT0];
  358.     lint.masked = true;
  359.     l_apic[LVT_LINT0] = lint.value;
  360.  
  361.     /* Initialize LVT LINT1 register. */
  362.     lint.value = l_apic[LVT_LINT1];
  363.     lint.masked = true;
  364.     l_apic[LVT_LINT1] = lint.value;
  365.  
  366.     /* Task Priority Register initialization. */
  367.     tpr.value = l_apic[TPR];
  368.     tpr.pri_sc = 0;
  369.     tpr.pri = 0;
  370.     l_apic[TPR] = tpr.value;
  371.    
  372.     /* Spurious-Interrupt Vector Register initialization. */
  373.     svr.value = l_apic[SVR];
  374.     svr.vector = VECTOR_APIC_SPUR;
  375.     svr.lapic_enabled = true;
  376.     svr.focus_checking = true;
  377.     l_apic[SVR] = svr.value;
  378.  
  379.     if (CPU->arch.family >= 6)
  380.         enable_l_apic_in_msr();
  381.    
  382.     /* Interrupt Command Register initialization. */
  383.     icr.lo = l_apic[ICRlo];
  384.     icr.delmod = DELMOD_INIT;
  385.     icr.destmod = DESTMOD_PHYS;
  386.     icr.level = LEVEL_DEASSERT;
  387.     icr.shorthand = SHORTHAND_ALL_INCL;
  388.     icr.trigger_mode = TRIGMOD_LEVEL;
  389.     l_apic[ICRlo] = icr.lo;
  390.    
  391.     /* Timer Divide Configuration Register initialization. */
  392.     tdcr.value = l_apic[TDCR];
  393.     tdcr.div_value = DIVIDE_1;
  394.     l_apic[TDCR] = tdcr.value;
  395.  
  396.     /* Program local timer. */
  397.     tm.value = l_apic[LVT_Tm];
  398.     tm.vector = VECTOR_CLK;
  399.     tm.mode = TIMER_PERIODIC;
  400.     tm.masked = false;
  401.     l_apic[LVT_Tm] = tm.value;
  402.  
  403.     /*
  404.      * Measure and configure the timer to generate timer
  405.      * interrupt with period 1s/HZ seconds.
  406.      */
  407.     t1 = l_apic[CCRT];
  408.     l_apic[ICRT] = 0xffffffff;
  409.  
  410.     while (l_apic[CCRT] == t1)
  411.         ;
  412.        
  413.     t1 = l_apic[CCRT];
  414.     delay(1000000/HZ);
  415.     t2 = l_apic[CCRT];
  416.    
  417.     l_apic[ICRT] = t1-t2;
  418.    
  419.     /* Program Logical Destination Register. */
  420.     ldr.value = l_apic[LDR];
  421.     if (CPU->id < sizeof(CPU->id)*8)    /* size in bits */
  422.         ldr.id = (1<<CPU->id);
  423.     l_apic[LDR] = ldr.value;
  424.    
  425.     /* Program Destination Format Register for Flat mode. */
  426.     dfr.value = l_apic[DFR];
  427.     dfr.model = MODEL_FLAT;
  428.     l_apic[DFR] = dfr.value;
  429. }
  430.  
  431. /** Local APIC End of Interrupt. */
  432. void l_apic_eoi(void)
  433. {
  434.     l_apic[EOI] = 0;
  435. }
  436.  
  437. /** Dump content of Local APIC registers. */
  438. void l_apic_debug(void)
  439. {
  440. #ifdef LAPIC_VERBOSE
  441.     lvt_tm_t tm;
  442.     lvt_lint_t lint;
  443.     lvt_error_t error; 
  444.    
  445.     printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
  446.  
  447.     tm.value = l_apic[LVT_Tm];
  448.     printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
  449.     lint.value = l_apic[LVT_LINT0];
  450.     printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
  451.     lint.value = l_apic[LVT_LINT1];
  452.     printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); 
  453.     error.value = l_apic[LVT_Err];
  454.     printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
  455. #endif
  456. }
  457.  
  458. /** Get Local APIC ID.
  459.  *
  460.  * @return Local APIC ID.
  461.  */
  462. uint8_t l_apic_id(void)
  463. {
  464.     l_apic_id_t idreg;
  465.    
  466.     idreg.value = l_apic[L_APIC_ID];
  467.     return idreg.apic_id;
  468. }
  469.  
  470. /** Read from IO APIC register.
  471.  *
  472.  * @param address IO APIC register address.
  473.  *
  474.  * @return Content of the addressed IO APIC register.
  475.  */
  476. uint32_t io_apic_read(uint8_t address)
  477. {
  478.     io_regsel_t regsel;
  479.    
  480.     regsel.value = io_apic[IOREGSEL];
  481.     regsel.reg_addr = address;
  482.     io_apic[IOREGSEL] = regsel.value;
  483.     return io_apic[IOWIN];
  484. }
  485.  
  486. /** Write to IO APIC register.
  487.  *
  488.  * @param address IO APIC register address.
  489.  * @param x Content to be written to the addressed IO APIC register.
  490.  */
  491. void io_apic_write(uint8_t address, uint32_t x)
  492. {
  493.     io_regsel_t regsel;
  494.    
  495.     regsel.value = io_apic[IOREGSEL];
  496.     regsel.reg_addr = address;
  497.     io_apic[IOREGSEL] = regsel.value;
  498.     io_apic[IOWIN] = x;
  499. }
  500.  
  501. /** Change some attributes of one item in I/O Redirection Table.
  502.  *
  503.  * @param pin IO APIC pin number.
  504.  * @param dest Interrupt destination address.
  505.  * @param v Interrupt vector to trigger.
  506.  * @param flags Flags.
  507.  */
  508. void io_apic_change_ioredtbl(int pin, int dest, uint8_t v, int flags)
  509. {
  510.     io_redirection_reg_t reg;
  511.     int dlvr = DELMOD_FIXED;
  512.    
  513.     if (flags & LOPRI)
  514.         dlvr = DELMOD_LOWPRI;
  515.  
  516.     reg.lo = io_apic_read(IOREDTBL + pin*2);
  517.     reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);
  518.    
  519.     reg.dest = dest;
  520.     reg.destmod = DESTMOD_LOGIC;
  521.     reg.trigger_mode = TRIGMOD_EDGE;
  522.     reg.intpol = POLARITY_HIGH;
  523.     reg.delmod = dlvr;
  524.     reg.intvec = v;
  525.  
  526.     io_apic_write(IOREDTBL + pin*2, reg.lo);
  527.     io_apic_write(IOREDTBL + pin*2 + 1, reg.hi);
  528. }
  529.  
  530. /** Mask IRQs in IO APIC.
  531.  *
  532.  * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
  533.  */
  534. void io_apic_disable_irqs(uint16_t irqmask)
  535. {
  536.     io_redirection_reg_t reg;
  537.     unsigned int i;
  538.     int pin;
  539.    
  540.     for (i = 0; i < 16; i++) {
  541.         if (irqmask & (1 << i)) {
  542.             /*
  543.              * Mask the signal input in IO APIC if there is a
  544.              * mapping for the respective IRQ number.
  545.              */
  546.             pin = smp_irq_to_pin(i);
  547.             if (pin != -1) {
  548.                 reg.lo = io_apic_read(IOREDTBL + pin * 2);
  549.                 reg.masked = true;
  550.                 io_apic_write(IOREDTBL + pin * 2, reg.lo);
  551.             }
  552.            
  553.         }
  554.     }
  555. }
  556.  
  557. /** Unmask IRQs in IO APIC.
  558.  *
  559.  * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
  560.  */
  561. void io_apic_enable_irqs(uint16_t irqmask)
  562. {
  563.     unsigned int i;
  564.     int pin;
  565.     io_redirection_reg_t reg;  
  566.    
  567.     for (i = 0;i < 16; i++) {
  568.         if (irqmask & (1 << i)) {
  569.             /*
  570.              * Unmask the signal input in IO APIC if there is a
  571.              * mapping for the respective IRQ number.
  572.              */
  573.             pin = smp_irq_to_pin(i);
  574.             if (pin != -1) {
  575.                 reg.lo = io_apic_read(IOREDTBL + pin * 2);
  576.                 reg.masked = false;
  577.                 io_apic_write(IOREDTBL + pin * 2, reg.lo);
  578.             }
  579.            
  580.         }
  581.     }
  582. }
  583.  
  584. #endif /* CONFIG_SMP */
  585.  
  586. /** @}
  587.  */
  588.