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  1. /*
  2.  * Copyright (C) 2001-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #include <arch/types.h>
  30. #include <arch/smp/apic.h>
  31. #include <arch/smp/ap.h>
  32. #include <arch/smp/mps.h>
  33. #include <arch/boot/boot.h>
  34. #include <mm/page.h>
  35. #include <time/delay.h>
  36. #include <interrupt.h>
  37. #include <arch/interrupt.h>
  38. #include <print.h>
  39. #include <arch/asm.h>
  40. #include <arch.h>
  41.  
  42. #ifdef CONFIG_SMP
  43.  
  44. /*
  45.  * Advanced Programmable Interrupt Controller for SMP systems.
  46.  * Tested on:
  47.  *  Bochs 2.0.2 - Bochs 2.2.5 with 2-8 CPUs
  48.  *  Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
  49.  *  VMware Workstation 5.5 with 2 CPUs
  50.  *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
  51.  *  ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
  52.  *  MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
  53.  */
  54.  
  55. /*
  56.  * These variables either stay configured as initilalized, or are changed by
  57.  * the MP configuration code.
  58.  *
  59.  * Pay special attention to the volatile keyword. Without it, gcc -O2 would
  60.  * optimize the code too much and accesses to l_apic and io_apic, that must
  61.  * always be 32-bit, would use byte oriented instructions.
  62.  */
  63. volatile __u32 *l_apic = (__u32 *) 0xfee00000;
  64. volatile __u32 *io_apic = (__u32 *) 0xfec00000;
  65.  
  66. __u32 apic_id_mask = 0;
  67.  
  68. static int apic_poll_errors(void);
  69.  
  70. #ifdef LAPIC_VERBOSE
  71. static char *delmod_str[] = {
  72.     "Fixed",
  73.     "Lowest Priority",
  74.     "SMI",
  75.     "Reserved",
  76.     "NMI",
  77.     "INIT",
  78.     "STARTUP",
  79.     "ExtInt"
  80. };
  81.  
  82. static char *destmod_str[] = {
  83.     "Physical",
  84.     "Logical"
  85. };
  86.  
  87. static char *trigmod_str[] = {
  88.     "Edge",
  89.     "Level"
  90. };
  91.  
  92. static char *mask_str[] = {
  93.     "Unmasked",
  94.     "Masked"
  95. };
  96.  
  97. static char *delivs_str[] = {
  98.     "Idle",
  99.     "Send Pending"
  100. };
  101.  
  102. static char *tm_mode_str[] = {
  103.     "One-shot",
  104.     "Periodic"
  105. };
  106.  
  107. static char *intpol_str[] = {
  108.     "Polarity High",
  109.     "Polarity Low"
  110. };
  111. #endif /* LAPIC_VERBOSE */
  112.  
  113.  
  114. static void apic_spurious(int n, void *stack);
  115. static void l_apic_timer_interrupt(int n, void *stack);
  116.  
  117. /** Initialize APIC on BSP. */
  118. void apic_init(void)
  119. {
  120.     io_apic_id_t idreg;
  121.     int i;
  122.  
  123.     exc_register(VECTOR_APIC_SPUR, "apic_spurious", apic_spurious);
  124.  
  125.     enable_irqs_function = io_apic_enable_irqs;
  126.     disable_irqs_function = io_apic_disable_irqs;
  127.     eoi_function = l_apic_eoi;
  128.    
  129.     /*
  130.      * Configure interrupt routing.
  131.      * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
  132.      * Other interrupts will be forwarded to the lowest priority CPU.
  133.      */
  134.     io_apic_disable_irqs(0xffff);
  135.     exc_register(VECTOR_CLK, "l_apic_timer", l_apic_timer_interrupt);
  136.     for (i = 0; i < IRQ_COUNT; i++) {
  137.         int pin;
  138.    
  139.         if ((pin = smp_irq_to_pin(i)) != -1) {
  140.             io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);
  141.         }
  142.     }
  143.    
  144.     /*
  145.      * Ensure that io_apic has unique ID.
  146.      */
  147.     idreg.value = io_apic_read(IOAPICID);
  148.     if ((1<<idreg.apic_id) & apic_id_mask) {    /* see if IO APIC ID is used already */
  149.         for (i = 0; i < APIC_ID_COUNT; i++) {
  150.             if (!((1<<i) & apic_id_mask)) {
  151.                 idreg.apic_id = i;
  152.                 io_apic_write(IOAPICID, idreg.value);
  153.                 break;
  154.             }
  155.         }
  156.     }
  157.  
  158.     /*
  159.      * Configure the BSP's lapic.
  160.      */
  161.     l_apic_init();
  162.  
  163.     l_apic_debug();
  164. }
  165.  
  166. /** APIC spurious interrupt handler.
  167.  *
  168.  * @param n Interrupt vector.
  169.  * @param stack Interrupted stack.
  170.  */
  171. void apic_spurious(int n, void *stack)
  172. {
  173.     printf("cpu%d: APIC spurious interrupt\n", CPU->id);
  174. }
  175.  
  176. /** Poll for APIC errors.
  177.  *
  178.  * Examine Error Status Register and report all errors found.
  179.  *
  180.  * @return 0 on error, 1 on success.
  181.  */
  182. int apic_poll_errors(void)
  183. {
  184.     esr_t esr;
  185.    
  186.     esr.value = l_apic[ESR];
  187.    
  188.     if (esr.send_checksum_error)
  189.         printf("Send Checksum Error\n");
  190.     if (esr.receive_checksum_error)
  191.         printf("Receive Checksum Error\n");
  192.     if (esr.send_accept_error)
  193.         printf("Send Accept Error\n");
  194.     if (esr.receive_accept_error)
  195.         printf("Receive Accept Error\n");
  196.     if (esr.send_illegal_vector)
  197.         printf("Send Illegal Vector\n");
  198.     if (esr.received_illegal_vector)
  199.         printf("Received Illegal Vector\n");
  200.     if (esr.illegal_register_address)
  201.         printf("Illegal Register Address\n");
  202.  
  203.     return !esr.err_bitmap;
  204. }
  205.  
  206. /** Send all CPUs excluding CPU IPI vector.
  207.  *
  208.  * @param vector Interrupt vector to be sent.
  209.  *
  210.  * @return 0 on failure, 1 on success.
  211.  */
  212. int l_apic_broadcast_custom_ipi(__u8 vector)
  213. {
  214.     icr_t icr;
  215.  
  216.     icr.lo = l_apic[ICRlo];
  217.     icr.delmod = DELMOD_FIXED;
  218.     icr.destmod = DESTMOD_LOGIC;
  219.     icr.level = LEVEL_ASSERT;
  220.     icr.shorthand = SHORTHAND_ALL_EXCL;
  221.     icr.trigger_mode = TRIGMOD_LEVEL;
  222.     icr.vector = vector;
  223.  
  224.     l_apic[ICRlo] = icr.lo;
  225.  
  226.     icr.lo = l_apic[ICRlo];
  227.     if (icr.delivs == DELIVS_PENDING)
  228.         printf("IPI is pending.\n");
  229.  
  230.     return apic_poll_errors();
  231. }
  232.  
  233. /** Universal Start-up Algorithm for bringing up the AP processors.
  234.  *
  235.  * @param apicid APIC ID of the processor to be brought up.
  236.  *
  237.  * @return 0 on failure, 1 on success.
  238.  */
  239. int l_apic_send_init_ipi(__u8 apicid)
  240. {
  241.     icr_t icr;
  242.     int i;
  243.  
  244.     /*
  245.      * Read the ICR register in and zero all non-reserved fields.
  246.      */
  247.     icr.lo = l_apic[ICRlo];
  248.     icr.hi = l_apic[ICRhi];
  249.    
  250.     icr.delmod = DELMOD_INIT;
  251.     icr.destmod = DESTMOD_PHYS;
  252.     icr.level = LEVEL_ASSERT;
  253.     icr.trigger_mode = TRIGMOD_LEVEL;
  254.     icr.shorthand = SHORTHAND_NONE;
  255.     icr.vector = 0;
  256.     icr.dest = apicid;
  257.    
  258.     l_apic[ICRhi] = icr.hi;
  259.     l_apic[ICRlo] = icr.lo;
  260.  
  261.     /*
  262.      * According to MP Specification, 20us should be enough to
  263.      * deliver the IPI.
  264.      */
  265.     delay(20);
  266.  
  267.     if (!apic_poll_errors()) return 0;
  268.  
  269.     icr.lo = l_apic[ICRlo];
  270.     if (icr.delivs == DELIVS_PENDING)
  271.         printf("IPI is pending.\n");
  272.  
  273.     icr.delmod = DELMOD_INIT;
  274.     icr.destmod = DESTMOD_PHYS;
  275.     icr.level = LEVEL_DEASSERT;
  276.     icr.shorthand = SHORTHAND_NONE;
  277.     icr.trigger_mode = TRIGMOD_LEVEL;
  278.     icr.vector = 0;
  279.     l_apic[ICRlo] = icr.lo;
  280.  
  281.     /*
  282.      * Wait 10ms as MP Specification specifies.
  283.      */
  284.     delay(10000);
  285.  
  286.     if (!is_82489DX_apic(l_apic[LAVR])) {
  287.         /*
  288.          * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
  289.          */
  290.         for (i = 0; i<2; i++) {
  291.             icr.lo = l_apic[ICRlo];
  292.             icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */
  293.             icr.delmod = DELMOD_STARTUP;
  294.             icr.destmod = DESTMOD_PHYS;
  295.             icr.level = LEVEL_ASSERT;
  296.             icr.shorthand = SHORTHAND_NONE;
  297.             icr.trigger_mode = TRIGMOD_LEVEL;
  298.             l_apic[ICRlo] = icr.lo;
  299.             delay(200);
  300.         }
  301.     }
  302.    
  303.     return apic_poll_errors();
  304. }
  305.  
  306. /** Initialize Local APIC. */
  307. void l_apic_init(void)
  308. {
  309.     lvt_error_t error;
  310.     lvt_lint_t lint;
  311.     svr_t svr;
  312.     icr_t icr;
  313.     tdcr_t tdcr;
  314.     lvt_tm_t tm;
  315.     ldr_t ldr;
  316.     dfr_t dfr;
  317.     __u32 t1, t2;
  318.  
  319.     /* Initialize LVT Error register. */
  320.     error.value = l_apic[LVT_Err];
  321.     error.masked = true;
  322.     l_apic[LVT_Err] = error.value;
  323.  
  324.     /* Initialize LVT LINT0 register. */
  325.     lint.value = l_apic[LVT_LINT0];
  326.     lint.masked = true;
  327.     l_apic[LVT_LINT0] = lint.value;
  328.  
  329.     /* Initialize LVT LINT1 register. */
  330.     lint.value = l_apic[LVT_LINT1];
  331.     lint.masked = true;
  332.     l_apic[LVT_LINT1] = lint.value;
  333.    
  334.     /* Spurious-Interrupt Vector Register initialization. */
  335.     svr.value = l_apic[SVR];
  336.     svr.vector = VECTOR_APIC_SPUR;
  337.     svr.lapic_enabled = true;
  338.     l_apic[SVR] = svr.value;
  339.  
  340.     l_apic[TPR] &= TPRClear;
  341.  
  342.     if (CPU->arch.family >= 6)
  343.         enable_l_apic_in_msr();
  344.    
  345.     /* Interrupt Command Register initialization. */
  346.     icr.lo = l_apic[ICRlo];
  347.     icr.delmod = DELMOD_INIT;
  348.     icr.destmod = DESTMOD_PHYS;
  349.     icr.level = LEVEL_DEASSERT;
  350.     icr.shorthand = SHORTHAND_ALL_INCL;
  351.     icr.trigger_mode = TRIGMOD_LEVEL;
  352.     l_apic[ICRlo] = icr.lo;
  353.    
  354.     /* Timer Divide Configuration Register initialization. */
  355.     tdcr.value = l_apic[TDCR];
  356.     tdcr.div_value = DIVIDE_1;
  357.     l_apic[TDCR] = tdcr.value;
  358.  
  359.     /* Program local timer. */
  360.     tm.value = l_apic[LVT_Tm];
  361.     tm.vector = VECTOR_CLK;
  362.     tm.mode = TIMER_PERIODIC;
  363.     tm.masked = false;
  364.     l_apic[LVT_Tm] = tm.value;
  365.  
  366.     /* Measure and configure the timer to generate timer interrupt each ms. */
  367.     t1 = l_apic[CCRT];
  368.     l_apic[ICRT] = 0xffffffff;
  369.  
  370.     while (l_apic[CCRT] == t1)
  371.         ;
  372.        
  373.     t1 = l_apic[CCRT];
  374.     delay(1000);
  375.     t2 = l_apic[CCRT];
  376.    
  377.     l_apic[ICRT] = t1-t2;
  378.    
  379.     /* Program Logical Destination Register. */
  380.     ldr.value = l_apic[LDR];
  381.     if (CPU->id < sizeof(CPU->id)*8)    /* size in bits */
  382.         ldr.id = (1<<CPU->id);
  383.     l_apic[LDR] = ldr.value;
  384.    
  385.     /* Program Destination Format Register for Flat mode. */
  386.     dfr.value = l_apic[DFR];
  387.     dfr.model = MODEL_FLAT;
  388.     l_apic[DFR] = dfr.value;
  389. }
  390.  
  391. /** Local APIC End of Interrupt. */
  392. void l_apic_eoi(void)
  393. {
  394.     l_apic[EOI] = 0;
  395. }
  396.  
  397. /** Dump content of Local APIC registers. */
  398. void l_apic_debug(void)
  399. {
  400. #ifdef LAPIC_VERBOSE
  401.     lvt_tm_t tm;
  402.     lvt_lint_t lint;
  403.     lvt_error_t error; 
  404.    
  405.     printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
  406.  
  407.     tm.value = l_apic[LVT_Tm];
  408.     printf("LVT Tm: vector=%B, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
  409.     lint.value = l_apic[LVT_LINT0];
  410.     printf("LVT LINT0: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
  411.     lint.value = l_apic[LVT_LINT1];
  412.     printf("LVT LINT1: vector=%B, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);   
  413.     error.value = l_apic[LVT_Err];
  414.     printf("LVT Err: vector=%B, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
  415. #endif
  416. }
  417.  
  418. /** Local APIC Timer Interrupt.
  419.  *
  420.  * @param n Interrupt vector number.
  421.  * @param stack Interrupted stack.
  422.  */
  423. void l_apic_timer_interrupt(int n, void *stack)
  424. {
  425.     l_apic_eoi();
  426.     clock();
  427. }
  428.  
  429. /** Get Local APIC ID.
  430.  *
  431.  * @return Local APIC ID.
  432.  */
  433. __u8 l_apic_id(void)
  434. {
  435.     l_apic_id_t idreg;
  436.    
  437.     idreg.value = l_apic[L_APIC_ID];
  438.     return idreg.apic_id;
  439. }
  440.  
  441. /** Read from IO APIC register.
  442.  *
  443.  * @param address IO APIC register address.
  444.  *
  445.  * @return Content of the addressed IO APIC register.
  446.  */
  447. __u32 io_apic_read(__u8 address)
  448. {
  449.     io_regsel_t regsel;
  450.    
  451.     regsel.value = io_apic[IOREGSEL];
  452.     regsel.reg_addr = address;
  453.     io_apic[IOREGSEL] = regsel.value;
  454.     return io_apic[IOWIN];
  455. }
  456.  
  457. /** Write to IO APIC register.
  458.  *
  459.  * @param address IO APIC register address.
  460.  * @param Content to be written to the addressed IO APIC register.
  461.  */
  462. void io_apic_write(__u8 address, __u32 x)
  463. {
  464.     io_regsel_t regsel;
  465.    
  466.     regsel.value = io_apic[IOREGSEL];
  467.     regsel.reg_addr = address;
  468.     io_apic[IOREGSEL] = regsel.value;
  469.     io_apic[IOWIN] = x;
  470. }
  471.  
  472. /** Change some attributes of one item in I/O Redirection Table.
  473.  *
  474.  * @param pin IO APIC pin number.
  475.  * @param dest Interrupt destination address.
  476.  * @param v Interrupt vector to trigger.
  477.  * @param flags Flags.
  478.  */
  479. void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags)
  480. {
  481.     io_redirection_reg_t reg;
  482.     int dlvr = DELMOD_FIXED;
  483.    
  484.     if (flags & LOPRI)
  485.         dlvr = DELMOD_LOWPRI;
  486.  
  487.     reg.lo = io_apic_read(IOREDTBL + pin*2);
  488.     reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);
  489.    
  490.     reg.dest = dest;
  491.     reg.destmod = DESTMOD_LOGIC;
  492.     reg.trigger_mode = TRIGMOD_EDGE;
  493.     reg.intpol = POLARITY_HIGH;
  494.     reg.delmod = dlvr;
  495.     reg.intvec = v;
  496.  
  497.     io_apic_write(IOREDTBL + pin*2, reg.lo);
  498.     io_apic_write(IOREDTBL + pin*2 + 1, reg.hi);
  499. }
  500.  
  501. /** Mask IRQs in IO APIC.
  502.  *
  503.  * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
  504.  */
  505. void io_apic_disable_irqs(__u16 irqmask)
  506. {
  507.     io_redirection_reg_t reg;
  508.     int i, pin;
  509.    
  510.     for (i=0;i<16;i++) {
  511.         if (irqmask & (1<<i)) {
  512.             /*
  513.              * Mask the signal input in IO APIC if there is a
  514.              * mapping for the respective IRQ number.
  515.              */
  516.             pin = smp_irq_to_pin(i);
  517.             if (pin != -1) {
  518.                 reg.lo = io_apic_read(IOREDTBL + pin*2);
  519.                 reg.masked = true;
  520.                 io_apic_write(IOREDTBL + pin*2, reg.lo);
  521.             }
  522.            
  523.         }
  524.     }
  525. }
  526.  
  527. /** Unmask IRQs in IO APIC.
  528.  *
  529.  * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
  530.  */
  531. void io_apic_enable_irqs(__u16 irqmask)
  532. {
  533.     int i, pin;
  534.     io_redirection_reg_t reg;  
  535.    
  536.     for (i=0;i<16;i++) {
  537.         if (irqmask & (1<<i)) {
  538.             /*
  539.              * Unmask the signal input in IO APIC if there is a
  540.              * mapping for the respective IRQ number.
  541.              */
  542.             pin = smp_irq_to_pin(i);
  543.             if (pin != -1) {
  544.                 reg.lo = io_apic_read(IOREDTBL + pin*2);
  545.                 reg.masked = false;
  546.                 io_apic_write(IOREDTBL + pin*2, reg.lo);
  547.             }
  548.            
  549.         }
  550.     }
  551. }
  552.  
  553. #endif /* CONFIG_SMP */
  554.