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  1. /*
  2.  * Copyright (C) 2001-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #include <arch/types.h>
  30. #include <arch/smp/apic.h>
  31. #include <arch/smp/ap.h>
  32. #include <arch/smp/mps.h>
  33. #include <mm/page.h>
  34. #include <time/delay.h>
  35. #include <arch/interrupt.h>
  36. #include <print.h>
  37. #include <arch/asm.h>
  38. #include <arch.h>
  39.  
  40. #ifdef __SMP__
  41.  
  42. /*
  43.  * This is functional, far-from-general-enough interface to the APIC.
  44.  * Advanced Programmable Interrupt Controller for MP systems.
  45.  * Tested on:
  46.  *  Bochs 2.0.2 - Bochs 2.2-cvs with 2-8 CPUs
  47.  *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
  48.  */
  49.  
  50. /*
  51.  * These variables either stay configured as initilalized, or are changed by
  52.  * the MP configuration code.
  53.  *
  54.  * Pay special attention to the volatile keyword. Without it, gcc -O2 would
  55.  * optimize the code too much and accesses to l_apic and io_apic, that must
  56.  * always be 32-bit, would use byte oriented instructions.
  57.  */
  58. volatile __u32 *l_apic = (__u32 *) 0xfee00000;
  59. volatile __u32 *io_apic = (__u32 *) 0xfec00000;
  60.  
  61. __u32 apic_id_mask = 0;
  62.  
  63. int apic_poll_errors(void);
  64.  
  65. void apic_init(void)
  66. {
  67.     __u32 tmp, id, i;
  68.  
  69.     trap_register(VECTOR_APIC_SPUR, apic_spurious);
  70.  
  71.     enable_irqs_function = io_apic_enable_irqs;
  72.     disable_irqs_function = io_apic_disable_irqs;
  73.     eoi_function = l_apic_eoi;
  74.    
  75.     /*
  76.      * Configure interrupt routing.
  77.      * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
  78.      * Other interrupts will be forwarded to the lowest priority CPU.
  79.      */
  80.     io_apic_disable_irqs(0xffff);
  81.     trap_register(VECTOR_CLK, l_apic_timer_interrupt);
  82.     for (i=1; i<16; i++) {
  83.         int pin;
  84.    
  85.         if ((pin = mps_irq_to_pin(i)) != -1)
  86.                 io_apic_change_ioredtbl(pin,0xf,IVT_IRQBASE+i,LOPRI);
  87.     }
  88.    
  89.  
  90.     /*
  91.      * Ensure that io_apic has unique ID.
  92.      */
  93.     tmp = io_apic_read(IOAPICID);
  94.     id = (tmp >> 24) & 0xf;
  95.     if ((1<<id) & apic_id_mask) {
  96.         int i;
  97.        
  98.         for (i=0; i<15; i++) {
  99.             if (!((1<<i) & apic_id_mask)) {
  100.                 io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) | (i<<24));
  101.                 break;
  102.             }
  103.         }
  104.     }
  105.  
  106.     /*
  107.      * Configure the BSP's lapic.
  108.      */
  109.     l_apic_init();
  110.     l_apic_debug();
  111. }
  112.  
  113. void apic_spurious(__u8 n, __u32 stack[])
  114. {
  115.     printf("cpu%d: APIC spurious interrupt\n", CPU->id);
  116. }
  117.  
  118. int apic_poll_errors(void)
  119. {
  120.     __u32 esr;
  121.    
  122.     esr = l_apic[ESR] & ~ESRClear;
  123.    
  124.     if ((esr>>0) & 1)
  125.         printf("Send CS Error\n");
  126.     if ((esr>>1) & 1)
  127.         printf("Receive CS Error\n");
  128.     if ((esr>>2) & 1)
  129.         printf("Send Accept Error\n");
  130.     if ((esr>>3) & 1)
  131.         printf("Receive Accept Error\n");
  132.     if ((esr>>5) & 1)
  133.         printf("Send Illegal Vector\n");
  134.     if ((esr>>6) & 1)
  135.         printf("Received Illegal Vector\n");
  136.     if ((esr>>7) & 1)
  137.         printf("Illegal Register Address\n");
  138.    
  139.     return !esr;
  140. }
  141.  
  142. /*
  143.  * Send all CPUs excluding CPU IPI vector.
  144.  */
  145. int l_apic_broadcast_custom_ipi(__u8 vector)
  146. {
  147.     __u32 lo;
  148.  
  149.     /*
  150.      * Read the ICR register in and zero all non-reserved fields.
  151.      */
  152.     lo = l_apic[ICRlo] & ICRloClear;
  153.  
  154.     lo |= DLVRMODE_FIXED | DESTMODE_LOGIC | LEVEL_ASSERT | SHORTHAND_EXCL | TRGRMODE_LEVEL | vector;
  155.    
  156.     l_apic[ICRlo] = lo;
  157.  
  158.     lo = l_apic[ICRlo] & ICRloClear;
  159.     if (lo & SEND_PENDING)
  160.         printf("IPI is pending.\n");
  161.  
  162.     return apic_poll_errors();
  163. }
  164.  
  165. /*
  166.  * Universal Start-up Algorithm for bringing up the AP processors.
  167.  */
  168. int l_apic_send_init_ipi(__u8 apicid)
  169. {
  170.     __u32 lo, hi;
  171.     int i;
  172.  
  173.     /*
  174.      * Read the ICR register in and zero all non-reserved fields.
  175.      */
  176.     lo = l_apic[ICRlo] & ICRloClear;
  177.     hi = l_apic[ICRhi] & ICRhiClear;
  178.    
  179.     lo |= DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
  180.     hi |= apicid << 24;
  181.    
  182.     l_apic[ICRhi] = hi;
  183.     l_apic[ICRlo] = lo;
  184.  
  185.     /*
  186.      * According to MP Specification, 20us should be enough to
  187.      * deliver the IPI.
  188.      */
  189.     delay(20);
  190.  
  191.     if (!apic_poll_errors()) return 0;
  192.  
  193.     lo = l_apic[ICRlo] & ICRloClear;
  194.     if (lo & SEND_PENDING)
  195.         printf("IPI is pending.\n");
  196.  
  197.     l_apic[ICRlo] = lo | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
  198.  
  199.     /*
  200.      * Wait 10ms as MP Specification specifies.
  201.      */
  202.     delay(10000);
  203.  
  204.     if (!is_82489DX_apic(l_apic[LAVR])) {
  205.         /*
  206.          * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
  207.          */
  208.         for (i = 0; i<2; i++) {
  209.             lo = l_apic[ICRlo] & ICRloClear;
  210.             lo |= ((__address) ap_boot) / 4096; /* calculate the reset vector */
  211.             l_apic[ICRlo] = lo | DLVRMODE_STUP | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST |  TRGRMODE_LEVEL;
  212.             delay(200);
  213.         }
  214.     }
  215.    
  216.    
  217.     return apic_poll_errors();
  218. }
  219.  
  220. void l_apic_init(void)
  221. {
  222.     __u32 tmp, t1, t2;
  223.  
  224.     l_apic[LVT_Err] |= (1<<16);
  225.     l_apic[LVT_LINT0] |= (1<<16);
  226.     l_apic[LVT_LINT1] |= (1<<16);
  227.  
  228.     tmp = l_apic[SVR] & SVRClear;
  229.     l_apic[SVR] = tmp | (1<<8) | (VECTOR_APIC_SPUR);
  230.  
  231.     l_apic[TPR] &= TPRClear;
  232.  
  233.     if (CPU->arch.family >= 6)
  234.         enable_l_apic_in_msr();
  235.    
  236.     tmp = l_apic[ICRlo] & ICRloClear;
  237.     l_apic[ICRlo] = tmp | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_INCL | TRGRMODE_LEVEL;
  238.    
  239.     /*
  240.      * Program the timer for periodic mode and respective vector.
  241.      */
  242.  
  243.     l_apic[TDCR] &= TDCRClear;
  244.     l_apic[TDCR] |= 0xb;
  245.     tmp = l_apic[LVT_Tm] | (1<<17) | (VECTOR_CLK);
  246.     l_apic[LVT_Tm] = tmp & ~(1<<16);
  247.  
  248.     t1 = l_apic[CCRT];
  249.     l_apic[ICRT] = 0xffffffff;
  250.  
  251.     while (l_apic[CCRT] == t1)
  252.         ;
  253.        
  254.     t1 = l_apic[CCRT];
  255.     delay(1000);
  256.     t2 = l_apic[CCRT];
  257.    
  258.     l_apic[ICRT] = t1-t2;
  259.    
  260. }
  261.  
  262. void l_apic_eoi(void)
  263. {
  264.     l_apic[EOI] = 0;
  265. }
  266.  
  267. void l_apic_debug(void)
  268. {
  269. #ifdef LAPIC_VERBOSE
  270.     int i, lint;
  271.  
  272.     printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
  273.  
  274.     printf("LVT_Tm: ");
  275.     if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(',');   
  276.     if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
  277.     if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
  278.     printf("%B\n", l_apic[LVT_Tm] & 0xff);
  279.    
  280.     for (i=0; i<2; i++) {
  281.         lint = i ? LVT_LINT1 : LVT_LINT0;
  282.         printf("LVT_LINT%d: ", i);
  283.         if (l_apic[lint] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
  284.         if (l_apic[lint] & (1<<15)) printf("level"); else printf("edge"); putchar(',');
  285.         printf("%d", l_apic[lint] & (1<<14)); putchar(',');
  286.         printf("%d", l_apic[lint] & (1<<13)); putchar(',');
  287.         if (l_apic[lint] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
  288.    
  289.         switch ((l_apic[lint]>>8)&7) {
  290.             case 0: printf("fixed"); break;
  291.             case 4: printf("NMI"); break;
  292.             case 7: printf("ExtINT"); break;
  293.         }
  294.         putchar(',');
  295.         printf("%B\n", l_apic[lint] & 0xff);   
  296.     }
  297.  
  298.     printf("LVT_Err: ");
  299.     if (l_apic[LVT_Err] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
  300.     if (l_apic[LVT_Err] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
  301.     printf("%B\n", l_apic[LVT_Err] & 0xff);
  302.  
  303.     /*
  304.      * This register is supported only on P6 and higher.
  305.      */
  306.     if (CPU->arch.family > 5) {
  307.         printf("LVT_PCINT: ");
  308.         if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
  309.         if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
  310.         switch ((l_apic[LVT_PCINT] >> 8)&7) {
  311.             case 0: printf("fixed"); break;
  312.             case 4: printf("NMI"); break;
  313.             case 7: printf("ExtINT"); break;
  314.         }
  315.         putchar(',');
  316.         printf("%B\n", l_apic[LVT_PCINT] & 0xff);
  317.     }
  318. #endif
  319. }
  320.  
  321. void l_apic_timer_interrupt(__u8 n, __u32 stack[])
  322. {
  323.     l_apic_eoi();
  324.     clock();
  325. }
  326.  
  327. __u8 l_apic_id(void)
  328. {
  329.     return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask;
  330. }
  331.  
  332. __u32 io_apic_read(__u8 address)
  333. {
  334.     __u32 tmp;
  335.    
  336.     tmp = io_apic[IOREGSEL] & ~0xf;
  337.     io_apic[IOREGSEL] = tmp | address;
  338.     return io_apic[IOWIN];
  339. }
  340.  
  341. void io_apic_write(__u8 address, __u32 x)
  342. {
  343.     __u32 tmp;
  344.  
  345.     tmp = io_apic[IOREGSEL] & ~0xf;
  346.     io_apic[IOREGSEL] = tmp | address;
  347.     io_apic[IOWIN] = x;
  348. }
  349.  
  350. void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags)
  351. {
  352.     __u32 reglo, reghi;
  353.     int dlvr = 0;
  354.    
  355.     if (flags & LOPRI)
  356.         dlvr = 1;
  357.    
  358.     reglo = io_apic_read(IOREDTBL + signal*2);
  359.     reghi = io_apic_read(IOREDTBL + signal*2 + 1);
  360.    
  361.     reghi &= ~0x0f000000;
  362.     reghi |= (dest<<24);
  363.  
  364.     reglo &= (~0x1ffff) | (1<<16); /* don't touch the mask */
  365.     reglo |= (0<<15) | (0<<13) | (0<<11) | (dlvr<<8) | v;
  366.  
  367.     io_apic_write(IOREDTBL + signal*2, reglo);     
  368.     io_apic_write(IOREDTBL + signal*2 + 1, reghi);
  369. }
  370.  
  371. void io_apic_disable_irqs(__u16 irqmask)
  372. {
  373.     int i,pin;
  374.     __u32 reglo;
  375.    
  376.     for (i=0;i<16;i++) {
  377.         if ((irqmask>>i) & 1) {
  378.             /*
  379.              * Mask the signal input in IO APIC if there is a
  380.              * mapping for the respective IRQ number.
  381.              */
  382.             pin = mps_irq_to_pin(i);
  383.             if (pin != -1) {
  384.                 reglo = io_apic_read(IOREDTBL + pin*2);
  385.                 reglo |= (1<<16);
  386.                 io_apic_write(IOREDTBL + pin*2,reglo);
  387.             }
  388.            
  389.         }
  390.     }
  391. }
  392.  
  393. void io_apic_enable_irqs(__u16 irqmask)
  394. {
  395.     int i,pin;
  396.     __u32 reglo;
  397.    
  398.     for (i=0;i<16;i++) {
  399.         if ((irqmask>>i) & 1) {
  400.             /*
  401.              * Unmask the signal input in IO APIC if there is a
  402.              * mapping for the respective IRQ number.
  403.              */
  404.             pin = mps_irq_to_pin(i);
  405.             if (pin != -1) {
  406.                 reglo = io_apic_read(IOREDTBL + pin*2);
  407.                 reglo &= ~(1<<16);
  408.                 io_apic_write(IOREDTBL + pin*2,reglo);
  409.             }
  410.            
  411.         }
  412.     }
  413.  
  414. }
  415.  
  416. #endif /* __SMP__ */
  417.