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  1. /*
  2.  * Copyright (C) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #include <proc/scheduler.h>
  30. #include <cpu.h>
  31. #include <proc/task.h>
  32. #include <proc/thread.h>
  33. #include <arch.h>
  34. #include <arch/context.h>   /* SP_DELTA */
  35. #include <arch/debugger.h>
  36. #include <arch/pm.h>
  37. #include <arch/asm.h>
  38. #include <adt/bitmap.h>
  39. #include <print.h>
  40.  
  41. /** Perform ia32 specific tasks needed before the new task is run.
  42.  *
  43.  * Interrupts are disabled.
  44.  */
  45. void before_task_runs_arch(void)
  46. {
  47.     count_t bits;
  48.     ptr_16_32_t cpugdtr;
  49.     descriptor_t *gdt_p;
  50.  
  51.     /*
  52.      * Switch the I/O Permission Bitmap, if necessary.
  53.      */
  54.  
  55.     /* First, copy the I/O Permission Bitmap. */
  56.     spinlock_lock(&TASK->lock);
  57.     if ((bits = TASK->arch.iomap.bits)) {
  58.         bitmap_t iomap;
  59.    
  60.         ASSERT(TASK->arch.iomap.map);
  61.         bitmap_initialize(&iomap, CPU->arch.tss->iomap, TSS_IOMAP_SIZE * 8);
  62.         bitmap_copy(&iomap, &TASK->arch.iomap, TASK->arch.iomap.bits);
  63.         /*
  64.          * It is safe to set the trailing four bits because of the extra
  65.          * convenience byte in TSS_IOMAP_SIZE.
  66.          */
  67.         bitmap_set_range(&iomap, TASK->arch.iomap.bits, 4);
  68.     }
  69.     spinlock_unlock(&TASK->lock);
  70.  
  71.     /* Second, adjust TSS segment limit. */
  72.     gdtr_store(&cpugdtr);
  73.     gdt_p = (descriptor_t *) cpugdtr.base;
  74.     gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + BITS2BYTES(bits) - 1);
  75.     gdtr_load(&cpugdtr);
  76. }
  77.  
  78. /** Perform ia32 specific tasks needed before the new thread is scheduled.
  79.  *
  80.  * THREAD is locked and interrupts are disabled.
  81.  */
  82. void before_thread_runs_arch(void)
  83. {
  84.     CPU->arch.tss->esp0 = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
  85.     CPU->arch.tss->ss0 = selector(KDATA_DES);
  86.  
  87.     /* Set up TLS in GS register */
  88.     set_tls_desc(THREAD->arch.tls);
  89.  
  90. #ifdef CONFIG_DEBUG_AS_WATCHPOINT
  91.     /* Set watchpoint on AS to ensure that nobody sets it to zero */
  92.     if (CPU->id < BKPOINTS_MAX)
  93.         breakpoint_add(&((the_t *) THREAD->kstack)->as,
  94.                    BKPOINT_WRITE | BKPOINT_CHECK_ZERO,
  95.                    CPU->id);
  96. #endif
  97. }
  98.  
  99. void after_thread_ran_arch(void)
  100. {
  101. }
  102.