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  1. /*
  2.  * Copyright (c) 2001-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup ia32   
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #include <arch/pm.h>
  36. #include <config.h>
  37. #include <arch/types.h>
  38. #include <typedefs.h>
  39. #include <arch/interrupt.h>
  40. #include <arch/asm.h>
  41. #include <arch/context.h>
  42. #include <panic.h>
  43. #include <arch/mm/page.h>
  44. #include <mm/slab.h>
  45. #include <memstr.h>
  46. #include <arch/boot/boot.h>
  47. #include <interrupt.h>
  48.  
  49. /*
  50.  * Early ia32 configuration functions and data structures.
  51.  */
  52.  
  53. /*
  54.  * We have no use for segmentation so we set up flat mode. In this
  55.  * mode, we use, for each privilege level, two segments spanning the
  56.  * whole memory. One is for code and one is for data.
  57.  *
  58.  * One is for GS register which holds pointer to the TLS thread
  59.  * structure in it's base.
  60.  */
  61. descriptor_t gdt[GDT_ITEMS] = {
  62.     /* NULL descriptor */
  63.     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
  64.     /* KTEXT descriptor */
  65.     { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
  66.     /* KDATA descriptor */
  67.     { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
  68.     /* UTEXT descriptor */
  69.     { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
  70.     /* UDATA descriptor */
  71.     { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
  72.     /* TSS descriptor - set up will be completed later */
  73.     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
  74.     /* TLS descriptor */
  75.     { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
  76.     /* VESA Init descriptor */
  77. #ifdef CONFIG_FB
  78.     { 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
  79. #endif 
  80. };
  81.  
  82. static idescriptor_t idt[IDT_ITEMS];
  83.  
  84. static tss_t tss;
  85.  
  86. tss_t *tss_p = NULL;
  87.  
  88. /* gdtr is changed by kmp before next CPU is initialized */
  89. ptr_16_32_t bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((uintptr_t) gdt) };
  90. ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (uintptr_t) gdt };
  91.  
  92. void gdt_setbase(descriptor_t *d, uintptr_t base)
  93. {
  94.     d->base_0_15 = base & 0xffff;
  95.     d->base_16_23 = ((base) >> 16) & 0xff;
  96.     d->base_24_31 = ((base) >> 24) & 0xff;
  97. }
  98.  
  99. void gdt_setlimit(descriptor_t *d, uint32_t limit)
  100. {
  101.     d->limit_0_15 = limit & 0xffff;
  102.     d->limit_16_19 = (limit >> 16) & 0xf;
  103. }
  104.  
  105. void idt_setoffset(idescriptor_t *d, uintptr_t offset)
  106. {
  107.     /*
  108.      * Offset is a linear address.
  109.      */
  110.     d->offset_0_15 = offset & 0xffff;
  111.     d->offset_16_31 = offset >> 16;
  112. }
  113.  
  114. void tss_initialize(tss_t *t)
  115. {
  116.     memsetb((uintptr_t) t, sizeof(struct tss), 0);
  117. }
  118.  
  119. /*
  120.  * This function takes care of proper setup of IDT and IDTR.
  121.  */
  122. void idt_init(void)
  123. {
  124.     idescriptor_t *d;
  125.     int i;
  126.  
  127.     for (i = 0; i < IDT_ITEMS; i++) {
  128.         d = &idt[i];
  129.  
  130.         d->unused = 0;
  131.         d->selector = selector(KTEXT_DES);
  132.  
  133.         d->access = AR_PRESENT | AR_INTERRUPT;  /* masking interrupt */
  134.  
  135.         if (i == VECTOR_SYSCALL) {
  136.             /*
  137.              * The syscall interrupt gate must be calleable from userland.
  138.              */
  139.             d->access |= DPL_USER;
  140.         }
  141.        
  142.         idt_setoffset(d, ((uintptr_t) interrupt_handlers) + i * interrupt_handler_size);
  143.     }
  144. }
  145.  
  146.  
  147. /* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
  148. static void clean_IOPL_NT_flags(void)
  149. {
  150.     __asm__ volatile (
  151.         "pushfl\n"
  152.         "pop %%eax\n"
  153.         "and $0xffff8fff, %%eax\n"
  154.         "push %%eax\n"
  155.         "popfl\n"
  156.         : : : "eax"
  157.     );
  158. }
  159.  
  160. /* Clean AM(18) flag in CR0 register */
  161. static void clean_AM_flag(void)
  162. {
  163.     __asm__ volatile (
  164.         "mov %%cr0, %%eax\n"
  165.         "and $0xfffbffff, %%eax\n"
  166.         "mov %%eax, %%cr0\n"
  167.         : : : "eax"
  168.     );
  169. }
  170.  
  171. void pm_init(void)
  172. {
  173.     descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
  174.     ptr_16_32_t idtr;
  175.  
  176.     /*
  177.      * Update addresses in GDT and IDT to their virtual counterparts.
  178.      */
  179.     idtr.limit = sizeof(idt);
  180.     idtr.base = (uintptr_t) idt;
  181.     gdtr_load(&gdtr);
  182.     idtr_load(&idtr);
  183.    
  184.     /*
  185.      * Each CPU has its private GDT and TSS.
  186.      * All CPUs share one IDT.
  187.      */
  188.  
  189.     if (config.cpu_active == 1) {
  190.         idt_init();
  191.         /*
  192.          * NOTE: bootstrap CPU has statically allocated TSS, because
  193.          * the heap hasn't been initialized so far.
  194.          */
  195.         tss_p = &tss;
  196.     }
  197.     else {
  198.         tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
  199.         if (!tss_p)
  200.             panic("could not allocate TSS\n");
  201.     }
  202.  
  203.     tss_initialize(tss_p);
  204.    
  205.     gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
  206.     gdt_p[TSS_DES].special = 1;
  207.     gdt_p[TSS_DES].granularity = 0;
  208.    
  209.     gdt_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
  210.     gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
  211.  
  212.     /*
  213.      * As of this moment, the current CPU has its own GDT pointing
  214.      * to its own TSS. We just need to load the TR register.
  215.      */
  216.     tr_load(selector(TSS_DES));
  217.    
  218.     clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels and clear NT flag. */
  219.     clean_AM_flag();          /* Disable alignment check */
  220. }
  221.  
  222. void set_tls_desc(uintptr_t tls)
  223. {
  224.     ptr_16_32_t cpugdtr;
  225.     descriptor_t *gdt_p;
  226.  
  227.     gdtr_store(&cpugdtr);
  228.     gdt_p = (descriptor_t *) cpugdtr.base;
  229.     gdt_setbase(&gdt_p[TLS_DES], tls);
  230.     /* Reload gdt register to update GS in CPU */
  231.     gdtr_load(&cpugdtr);
  232. }
  233.  
  234. /** @}
  235.  */
  236.