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  1. /*
  2.  * Copyright (C) 2001-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #ifndef __ia32_ASM_H__
  30. #define __ia32_ASM_H__
  31.  
  32. #include <arch/types.h>
  33. #include <config.h>
  34.  
  35. extern __u32 interrupt_handler_size;
  36.  
  37. extern void paging_on(void);
  38.  
  39. extern void interrupt_handlers(void);
  40.  
  41. extern __u8 inb(int port);
  42. extern __u16 inw(int port);
  43. extern __u32 inl(int port);
  44.  
  45. extern void enable_l_apic_in_msr(void);
  46.  
  47.  
  48. void asm_delay_loop(__u32 t);
  49. void asm_fake_loop(__u32 t);
  50.  
  51.  
  52. /** Halt CPU
  53.  *
  54.  * Halt the current CPU until interrupt event.
  55.  */
  56. static inline void cpu_halt(void) { __asm__("hlt\n"); };
  57. static inline void cpu_sleep(void) { __asm__("hlt\n"); };
  58.  
  59. /** Read CR2
  60.  *
  61.  * Return value in CR2
  62.  *
  63.  * @return Value read.
  64.  */
  65. static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0\n" : "=r" (v)); return v; }
  66.  
  67. /** Write CR3
  68.  *
  69.  * Write value to CR3.
  70.  *
  71.  * @param v Value to be written.
  72.  */
  73. static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); }
  74.  
  75. /** Read CR3
  76.  *
  77.  * Return value in CR3
  78.  *
  79.  * @return Value read.
  80.  */
  81. static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0\n" : "=r" (v)); return v; }
  82.  
  83. /** Byte to port
  84.  *
  85.  * Output byte to port
  86.  *
  87.  * @param port Port to write to
  88.  * @param val Value to write
  89.  */
  90. static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
  91.  
  92. /** Word to port
  93.  *
  94.  * Output word to port
  95.  *
  96.  * @param port Port to write to
  97.  * @param val Value to write
  98.  */
  99. static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
  100.  
  101.  
  102.  
  103. /** Double word to port
  104.  *
  105.  * Output double word to port
  106.  *
  107.  * @param port Port to write to
  108.  * @param val Value to write
  109.  */
  110. static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
  111.  
  112. /** Set priority level low
  113.  *
  114.  * Enable interrupts and return previous
  115.  * value of EFLAGS.
  116.  */
  117. static inline pri_t cpu_priority_low(void) {
  118.     pri_t v;
  119.     __asm__ volatile (
  120.         "pushf\n"
  121.         "popl %0\n"
  122.         "sti\n"
  123.         : "=r" (v)
  124.     );
  125.     return v;
  126. }
  127.  
  128. /** Set priority level high
  129.  *
  130.  * Disable interrupts and return previous
  131.  * value of EFLAGS.
  132.  */
  133. static inline pri_t cpu_priority_high(void) {
  134.     pri_t v;
  135.     __asm__ volatile (
  136.         "pushf\n"
  137.         "popl %0\n"
  138.         "cli\n"
  139.         : "=r" (v)
  140.     );
  141.     return v;
  142. }
  143.  
  144. /** Restore priority level
  145.  *
  146.  * Restore EFLAGS.
  147.  */
  148. static inline void cpu_priority_restore(pri_t pri) {
  149.     __asm__ volatile (
  150.         "pushl %0\n"
  151.         "popf\n"
  152.         : : "r" (pri)
  153.     );
  154. }
  155.  
  156. /** Return raw priority level
  157.  *
  158.  * Return EFLAFS.
  159.  */
  160. static inline pri_t cpu_priority_read(void) {
  161.     pri_t v;
  162.     __asm__ volatile (
  163.         "pushf\n"
  164.         "popl %0\n"
  165.         : "=r" (v)
  166.     );
  167.     return v;
  168. }
  169.  
  170. /** Return base address of current stack
  171.  *
  172.  * Return the base address of the current stack.
  173.  * The stack is assumed to be STACK_SIZE bytes long.
  174.  * The stack must start on page boundary.
  175.  */
  176. static inline __address get_stack_base(void)
  177. {
  178.     __address v;
  179.    
  180.     __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
  181.    
  182.     return v;
  183. }
  184.  
  185. static inline __u64 rdtsc(void)
  186. {
  187.     __u64 v;
  188.    
  189.     __asm__ volatile("rdtsc\n" : "=A" (v));
  190.    
  191.     return v;
  192. }
  193.  
  194.  
  195. #endif
  196.