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  1. /*
  2.  * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup arm32mm
  30.  * @{
  31.  */
  32. /** @file
  33.  *  @brief Page fault related functions.
  34.  */
  35. #include <panic.h>
  36. #include <arch/exception.h>
  37. #include <arch/debug/print.h>
  38. #include <arch/mm/page_fault.h>
  39. #include <mm/as.h>
  40. #include <genarch/mm/page_pt.h>
  41. #include <arch.h>
  42. #include <interrupt.h>
  43.  
  44.  
  45. /** Returns value stored in fault status register.
  46.  *
  47.  *  @return Value stored in CP15 fault status register (FSR).
  48.  */
  49. static inline fault_status_t read_fault_status_register(void)
  50. {
  51.     fault_status_union_t fsu;
  52.  
  53.     // fault status is stored in CP15 register 5
  54.     asm volatile (
  55.         "mrc p15, 0, %0, c5, c0, 0"
  56.         : "=r"(fsu.dummy)
  57.     );
  58.     return fsu.fs;
  59. }
  60.  
  61.  
  62. /** Returns FAR (fault address register) content.
  63.  *
  64.  *  @return FAR (fault address register) content (address that caused a page fault)
  65.  */
  66. static inline uintptr_t read_fault_address_register(void)
  67. {
  68.     uintptr_t ret;
  69.    
  70.     // fault adress is stored in CP15 register 6
  71.     asm volatile (
  72.         "mrc p15, 0, %0, c6, c0, 0"
  73.         : "=r"(ret)
  74.     );
  75.     return ret;
  76. }
  77.  
  78.  
  79. /** Decides whether the instruction is load/store or not.
  80.  *
  81.  * @param instr Instruction
  82.  *
  83.  * @return true when instruction is load/store, false otherwise
  84.  */
  85. static inline bool is_load_store_instruction(instruction_t instr)
  86. {
  87.     // load store immediate offset
  88.     if (instr.type == 0x2) {
  89.         return true;
  90.     }
  91.  
  92.     // load store register offset
  93.     if (instr.type == 0x3 && instr.bit4 == 0) {
  94.         return true;
  95.     }
  96.  
  97.     // load store multiple
  98.     if (instr.type == 0x4) {
  99.         return true;
  100.     }
  101.  
  102.     // coprocessor load/store
  103.     if (instr.type == 0x6) {
  104.         return true;
  105.     }
  106.  
  107.     return false;
  108. }
  109.  
  110.  
  111. /** Decides whether the instructions is swap or not.
  112.  *
  113.  * @param instr Instruction
  114.  *
  115.  * @return true when instruction is swap, false otherwise
  116.  */
  117. static inline bool is_swap_instruction(instruction_t instr)
  118. {
  119.     // swap, swapb instruction
  120.     if (instr.type == 0x0 &&
  121.         (instr.opcode == 0x8 || instr.opcode == 0xa) &&
  122.         instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) {
  123.         return true;
  124.     }
  125.  
  126.     return false;
  127. }
  128.  
  129.  
  130. /** Decides whether read or write into memory is requested.
  131.  *
  132.  * @param instr_addr   Address of instruction which tries to access memory.
  133.  * @param badvaddr     Virtual address the instruction tries to access.
  134.  *
  135.  * @return Type of access into memory, PF_ACCESS_EXEC if no memory access is requested.
  136.  */
  137. static pf_access_t get_memory_access_type(uint32_t instr_addr, uintptr_t badvaddr)
  138. {  
  139.     instruction_union_t instr_union;
  140.     instr_union.pc = instr_addr;
  141.  
  142.     instruction_t instr = *(instr_union.instr);
  143.  
  144.     // undefined instructions
  145.     if (instr.condition == 0xf) {
  146.         panic("page_fault - instruction doesn't access memory (instr_code: %x, badvaddr:%x)",
  147.             instr, badvaddr);
  148.         return PF_ACCESS_EXEC;
  149.     }
  150.  
  151.     // load store instructions
  152.     if (is_load_store_instruction(instr)) {
  153.         if (instr.access == 1) {
  154.             return PF_ACCESS_READ;
  155.         } else {
  156.             return PF_ACCESS_WRITE;
  157.         }
  158.     }
  159.  
  160.     // swap, swpb instruction
  161.     if (is_swap_instruction(instr)) {
  162.         return PF_ACCESS_WRITE;
  163.     }
  164.  
  165.     panic("page_fault - instruction doesn't access memory (instr_code: %x, badvaddr:%x)",
  166.         instr, badvaddr);
  167.  
  168.     return PF_ACCESS_EXEC;
  169. }
  170.  
  171. /** Handles "data abort" exception (load or store at invalid address).
  172.  *
  173.  * @param exc_no    Exception number.
  174.  * @param istate    CPU state when exception occured.
  175.  */
  176. void data_abort(int exc_no, istate_t *istate)
  177. {
  178.     fault_status_t fsr = read_fault_status_register();
  179.     uintptr_t badvaddr = read_fault_address_register();
  180.  
  181.     pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
  182.    
  183.     int ret = as_page_fault(badvaddr, access, istate);
  184.  
  185.     if (ret == AS_PF_FAULT) {
  186.         print_istate(istate);
  187.         dprintf("page fault - pc: %x, va: %x, status: %x(%x), access:%d\n",
  188.             istate->pc, badvaddr, fsr.status, fsr, access);
  189.  
  190.         fault_if_from_uspace(istate, "Page fault: %#x", badvaddr);
  191.         panic("page fault\n");
  192.     }
  193. }
  194.  
  195. /** Handles "prefetch abort" exception (instruction couldn't be executed).
  196.  *
  197.  * @param exc_no    Exception number.
  198.  * @param istate    CPU state when exception occured.
  199.  */
  200. void prefetch_abort(int exc_no, istate_t *istate)
  201. {
  202.     int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);
  203.  
  204.     if (ret == AS_PF_FAULT) {
  205.         dprintf("prefetch_abort\n");
  206.         print_istate(istate);
  207.         panic("page fault - prefetch_abort at address: %x\n", istate->pc);
  208.     }
  209. }
  210.  
  211. /** @}
  212.  */
  213.  
  214.