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  1. /*
  2.  * Copyright (C) 2005 Ondrej Palkovsky
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup amd64
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #include <arch.h>
  36.  
  37. #include <arch/types.h>
  38.  
  39. #include <config.h>
  40.  
  41. #include <proc/thread.h>
  42. #include <arch/drivers/ega.h>
  43. #include <arch/drivers/vesa.h>
  44. #include <genarch/kbd/i8042.h>
  45. #include <arch/drivers/i8254.h>
  46. #include <arch/drivers/i8259.h>
  47.  
  48. #ifdef CONFIG_SMP
  49. #include <arch/smp/apic.h>
  50. #endif
  51.  
  52. #include <arch/bios/bios.h>
  53. #include <arch/mm/memory_init.h>
  54. #include <arch/cpu.h>
  55. #include <print.h>
  56. #include <arch/cpuid.h>
  57. #include <genarch/acpi/acpi.h>
  58. #include <panic.h>
  59. #include <interrupt.h>
  60. #include <arch/syscall.h>
  61. #include <arch/debugger.h>
  62. #include <syscall/syscall.h>
  63. #include <console/console.h>
  64.  
  65.  
  66. /** Disable I/O on non-privileged levels
  67.  *
  68.  * Clean IOPL(12,13) and NT(14) flags in EFLAGS register
  69.  */
  70. static void clean_IOPL_NT_flags(void)
  71. {
  72.     asm
  73.     (
  74.         "pushfq;"
  75.         "pop %%rax;"
  76.         "and $~(0x7000),%%rax;"
  77.         "pushq %%rax;"
  78.         "popfq;"
  79.         :
  80.         :
  81.         :"%rax"
  82.     );
  83. }
  84.  
  85. /** Disable alignment check
  86.  *
  87.  * Clean AM(18) flag in CR0 register
  88.  */
  89. static void clean_AM_flag(void)
  90. {
  91.     asm
  92.     (
  93.         "mov %%cr0,%%rax;"
  94.         "and $~(0x40000),%%rax;"
  95.         "mov %%rax,%%cr0;"
  96.         :
  97.         :
  98.         :"%rax"
  99.     );
  100. }
  101.  
  102. void arch_pre_mm_init(void)
  103. {
  104.     struct cpu_info cpuid_s;
  105.  
  106.     cpuid(AMD_CPUID_EXTENDED,&cpuid_s);
  107.     if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE)))
  108.         panic("Processor does not support No-execute pages.\n");
  109.  
  110.     cpuid(INTEL_CPUID_STANDARD,&cpuid_s);
  111.     if (! (cpuid_s.cpuid_edx & (1<<INTEL_FXSAVE)))
  112.         panic("Processor does not support FXSAVE/FXRESTORE.\n");
  113.    
  114.     if (! (cpuid_s.cpuid_edx & (1<<INTEL_SSE2)))
  115.         panic("Processor does not support SSE2 instructions.\n");
  116.  
  117.     /* Enable No-execute pages */
  118.     set_efer_flag(AMD_NXE_FLAG);
  119.     /* Enable FPU */
  120.     cpu_setup_fpu();
  121.  
  122.     /* Initialize segmentation */
  123.     pm_init();
  124.  
  125.         /* Disable I/O on nonprivileged levels
  126.      * clear the NT(nested-thread) flag
  127.      */
  128.     clean_IOPL_NT_flags();
  129.     /* Disable alignment check */
  130.     clean_AM_flag();
  131.  
  132.     if (config.cpu_active == 1) {
  133.         bios_init();
  134.         i8259_init();   /* PIC */
  135.         i8254_init();   /* hard clock */
  136.  
  137.         #ifdef CONFIG_SMP
  138.         exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown",
  139.                  tlb_shootdown_ipi);
  140.         #endif /* CONFIG_SMP */
  141.     }
  142. }
  143.  
  144. void arch_post_mm_init(void)
  145. {
  146.     if (config.cpu_active == 1) {
  147. #ifdef CONFIG_FB
  148.         if (vesa_present())
  149.             vesa_init();
  150.         else
  151. #endif
  152.             ega_init(); /* video */
  153.         /* Enable debugger */
  154.         debugger_init();
  155.         /* Merge all memory zones to 1 big zone */
  156.         zone_merge_all();
  157.     }
  158.     /* Setup fast SYSCALL/SYSRET */
  159.     syscall_setup_cpu();
  160.    
  161. }
  162.  
  163. void arch_post_cpu_init()
  164. {
  165. #ifdef CONFIG_SMP
  166.     if (config.cpu_active > 1) {
  167.         l_apic_init();
  168.         l_apic_debug();
  169.     }
  170. #endif
  171. }
  172.  
  173. void arch_pre_smp_init(void)
  174. {
  175.     if (config.cpu_active == 1) {
  176.         memory_print_map();
  177.        
  178.         #ifdef CONFIG_SMP
  179.         acpi_init();
  180.         #endif /* CONFIG_SMP */
  181.     }
  182. }
  183.  
  184. void arch_post_smp_init(void)
  185. {
  186.     i8042_init();   /* keyboard controller */
  187. }
  188.  
  189. void calibrate_delay_loop(void)
  190. {
  191.     i8254_calibrate_delay_loop();
  192.     i8254_normal_operation();
  193. }
  194.  
  195. /** Set thread-local-storage pointer
  196.  *
  197.  * TLS pointer is set in FS register. Unfortunately the 64-bit
  198.  * part can be set only in CPL0 mode.
  199.  *
  200.  * The specs say, that on %fs:0 there is stored contents of %fs register,
  201.  * we need not to go to CPL0 to read it.
  202.  */
  203. unative_t sys_tls_set(unative_t addr)
  204. {
  205.     THREAD->arch.tls = addr;
  206.     write_msr(AMD_MSR_FS, addr);
  207.     return 0;
  208. }
  209.  
  210. /** Acquire console back for kernel
  211.  *
  212.  */
  213. void arch_grab_console(void)
  214. {
  215.     i8042_grab();
  216. }
  217. /** Return console to userspace
  218.  *
  219.  */
  220. void arch_release_console(void)
  221. {
  222.     i8042_release();
  223. }
  224.  
  225. /** @}
  226.  */
  227.