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  1. /*
  2.  * Copyright (c) 2005 Ondrej Palkovsky
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup amd64
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #include <arch.h>
  36.  
  37. #include <arch/types.h>
  38.  
  39. #include <config.h>
  40.  
  41. #include <proc/thread.h>
  42. #include <arch/drivers/ega.h>
  43. #include <arch/drivers/vesa.h>
  44. #include <genarch/kbd/i8042.h>
  45. #include <arch/drivers/i8254.h>
  46. #include <arch/drivers/i8259.h>
  47.  
  48. #ifdef CONFIG_SMP
  49. #include <arch/smp/apic.h>
  50. #endif
  51.  
  52. #include <arch/bios/bios.h>
  53. #include <arch/mm/memory_init.h>
  54. #include <arch/cpu.h>
  55. #include <print.h>
  56. #include <arch/cpuid.h>
  57. #include <genarch/acpi/acpi.h>
  58. #include <panic.h>
  59. #include <interrupt.h>
  60. #include <arch/syscall.h>
  61. #include <arch/debugger.h>
  62. #include <syscall/syscall.h>
  63. #include <console/console.h>
  64. #include <ddi/irq.h>
  65. #include <ddi/device.h>
  66.  
  67.  
  68. /** Disable I/O on non-privileged levels
  69.  *
  70.  * Clean IOPL(12,13) and NT(14) flags in EFLAGS register
  71.  */
  72. static void clean_IOPL_NT_flags(void)
  73. {
  74.     asm (
  75.         "pushfq\n"
  76.         "pop %%rax\n"
  77.         "and $~(0x7000), %%rax\n"
  78.         "pushq %%rax\n"
  79.         "popfq\n"
  80.         :
  81.         :
  82.         : "%rax"
  83.     );
  84. }
  85.  
  86. /** Disable alignment check
  87.  *
  88.  * Clean AM(18) flag in CR0 register
  89.  */
  90. static void clean_AM_flag(void)
  91. {
  92.     asm (
  93.         "mov %%cr0, %%rax\n"
  94.         "and $~(0x40000), %%rax\n"
  95.         "mov %%rax, %%cr0\n"
  96.         :
  97.         :
  98.         : "%rax"
  99.     );
  100. }
  101.  
  102. void arch_pre_mm_init(void)
  103. {
  104.     /* Enable no-execute pages */
  105.     set_efer_flag(AMD_NXE_FLAG);
  106.     /* Enable FPU */
  107.     cpu_setup_fpu();
  108.  
  109.     /* Initialize segmentation */
  110.     pm_init();
  111.    
  112.     /* Disable I/O on nonprivileged levels
  113.      * clear the NT (nested-thread) flag
  114.      */
  115.     clean_IOPL_NT_flags();
  116.     /* Disable alignment check */
  117.     clean_AM_flag();
  118.  
  119.     if (config.cpu_active == 1) {
  120.         interrupt_init();
  121.         bios_init();
  122.        
  123.         /* PIC */
  124.         i8259_init();
  125.     }
  126. }
  127.  
  128.  
  129. void arch_post_mm_init(void)
  130. {
  131.     if (config.cpu_active == 1) {
  132.         /* Initialize IRQ routing */
  133.         irq_init(IRQ_COUNT, IRQ_COUNT);
  134.        
  135.         /* hard clock */
  136.         i8254_init();
  137.                
  138. #ifdef CONFIG_FB
  139.         if (vesa_present())
  140.             vesa_init();
  141.         else
  142. #endif
  143.             ega_init(); /* video */
  144.        
  145.         /* Enable debugger */
  146.         debugger_init();
  147.         /* Merge all memory zones to 1 big zone */
  148.         zone_merge_all();
  149.     }
  150.    
  151.     /* Setup fast SYSCALL/SYSRET */
  152.     syscall_setup_cpu();
  153. }
  154.  
  155. void arch_post_cpu_init()
  156. {
  157. #ifdef CONFIG_SMP
  158.     if (config.cpu_active > 1) {
  159.         l_apic_init();
  160.         l_apic_debug();
  161.     }
  162. #endif
  163. }
  164.  
  165. void arch_pre_smp_init(void)
  166. {
  167.     if (config.cpu_active == 1) {
  168.         memory_print_map();
  169.        
  170.         #ifdef CONFIG_SMP
  171.         acpi_init();
  172.         #endif /* CONFIG_SMP */
  173.     }
  174. }
  175.  
  176. void arch_post_smp_init(void)
  177. {
  178.     /* keyboard controller */
  179.     i8042_init(device_assign_devno(), IRQ_KBD, device_assign_devno(), IRQ_MOUSE);
  180. }
  181.  
  182. void calibrate_delay_loop(void)
  183. {
  184.     i8254_calibrate_delay_loop();
  185.     if (config.cpu_active == 1) {
  186.         /*
  187.          * This has to be done only on UP.
  188.          * On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.
  189.          */
  190.         i8254_normal_operation();
  191.     }
  192. }
  193.  
  194. /** Set thread-local-storage pointer
  195.  *
  196.  * TLS pointer is set in FS register. Unfortunately the 64-bit
  197.  * part can be set only in CPL0 mode.
  198.  *
  199.  * The specs say, that on %fs:0 there is stored contents of %fs register,
  200.  * we need not to go to CPL0 to read it.
  201.  */
  202. unative_t sys_tls_set(unative_t addr)
  203. {
  204.     THREAD->arch.tls = addr;
  205.     write_msr(AMD_MSR_FS, addr);
  206.     return 0;
  207. }
  208.  
  209. /** Acquire console back for kernel
  210.  *
  211.  */
  212. void arch_grab_console(void)
  213. {
  214.     i8042_grab();
  215. }
  216. /** Return console to userspace
  217.  *
  218.  */
  219. void arch_release_console(void)
  220. {
  221.     i8042_release();
  222. }
  223.  
  224. /** @}
  225.  */
  226.