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  1. /*
  2.  * Copyright (c) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup amd64  
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #ifndef KERN_amd64_ASM_H_
  36. #define KERN_amd64_ASM_H_
  37.  
  38. #include <config.h>
  39.  
  40. extern void asm_delay_loop(uint32_t t);
  41. extern void asm_fake_loop(uint32_t t);
  42.  
  43. /** Return base address of current stack.
  44.  *
  45.  * Return the base address of the current stack.
  46.  * The stack is assumed to be STACK_SIZE bytes long.
  47.  * The stack must start on page boundary.
  48.  */
  49. static inline uintptr_t get_stack_base(void)
  50. {
  51.     uintptr_t v;
  52.    
  53.     asm volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((uint64_t)STACK_SIZE-1)));
  54.    
  55.     return v;
  56. }
  57.  
  58. static inline void cpu_sleep(void)
  59. {
  60.     asm volatile ("hlt\n");
  61. }
  62.  
  63. static inline void cpu_halt(void)
  64. {
  65.     asm volatile ("hlt\n");
  66. }
  67.  
  68.  
  69. /** Byte from port
  70.  *
  71.  * Get byte from port
  72.  *
  73.  * @param port Port to read from
  74.  * @return Value read
  75.  */
  76. static inline uint8_t pio_read_8(ioport8_t *port)
  77. {
  78.     uint8_t val;
  79.  
  80.     asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port));
  81.     return val;
  82. }
  83.  
  84. /** Word from port
  85.  *
  86.  * Get word from port
  87.  *
  88.  * @param port Port to read from
  89.  * @return Value read
  90.  */
  91. static inline uint16_t pio_read_16(ioport16_t *port)
  92. {
  93.     uint16_t val;
  94.    
  95.     asm volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port));
  96.     return val;
  97. }
  98.  
  99. /** Double word from port
  100.  *
  101.  * Get double word from port
  102.  *
  103.  * @param port Port to read from
  104.  * @return Value read
  105.  */
  106. static inline uint32_t pio_read_32(ioport32_t *port)
  107. {
  108.     uint32_t val;
  109.    
  110.     asm volatile ("inl %w1, %0 \n" : "=a" (val) : "d" (port));
  111.     return val;
  112. }
  113.  
  114. /** Byte to port
  115.  *
  116.  * Output byte to port
  117.  *
  118.  * @param port Port to write to
  119.  * @param val Value to write
  120.  */
  121. static inline void pio_write_8(ioport8_t *port, uint8_t val)
  122. {
  123.     asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port));
  124. }
  125.  
  126. /** Word to port
  127.  *
  128.  * Output word to port
  129.  *
  130.  * @param port Port to write to
  131.  * @param val Value to write
  132.  */
  133. static inline void pio_write_16(ioport16_t *port, uint16_t val)
  134. {
  135.     asm volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port));
  136. }
  137.  
  138. /** Double word to port
  139.  *
  140.  * Output double word to port
  141.  *
  142.  * @param port Port to write to
  143.  * @param val Value to write
  144.  */
  145. static inline void pio_write_32(ioport32_t *port, uint32_t val)
  146. {
  147.     asm volatile ("outl %0, %w1\n" : : "a" (val), "d" (port));
  148. }
  149.  
  150. /** Swap Hidden part of GS register with visible one */
  151. static inline void swapgs(void)
  152. {
  153.     asm volatile("swapgs");
  154. }
  155.  
  156. /** Enable interrupts.
  157.  *
  158.  * Enable interrupts and return previous
  159.  * value of EFLAGS.
  160.  *
  161.  * @return Old interrupt priority level.
  162.  */
  163. static inline ipl_t interrupts_enable(void) {
  164.     ipl_t v;
  165.     __asm__ volatile (
  166.         "pushfq\n"
  167.         "popq %0\n"
  168.         "sti\n"
  169.         : "=r" (v)
  170.     );
  171.     return v;
  172. }
  173.  
  174. /** Disable interrupts.
  175.  *
  176.  * Disable interrupts and return previous
  177.  * value of EFLAGS.
  178.  *
  179.  * @return Old interrupt priority level.
  180.  */
  181. static inline ipl_t interrupts_disable(void) {
  182.     ipl_t v;
  183.     __asm__ volatile (
  184.         "pushfq\n"
  185.         "popq %0\n"
  186.         "cli\n"
  187.         : "=r" (v)
  188.         );
  189.     return v;
  190. }
  191.  
  192. /** Restore interrupt priority level.
  193.  *
  194.  * Restore EFLAGS.
  195.  *
  196.  * @param ipl Saved interrupt priority level.
  197.  */
  198. static inline void interrupts_restore(ipl_t ipl) {
  199.     __asm__ volatile (
  200.         "pushq %0\n"
  201.         "popfq\n"
  202.         : : "r" (ipl)
  203.         );
  204. }
  205.  
  206. /** Return interrupt priority level.
  207.  *
  208.  * Return EFLAFS.
  209.  *
  210.  * @return Current interrupt priority level.
  211.  */
  212. static inline ipl_t interrupts_read(void) {
  213.     ipl_t v;
  214.     __asm__ volatile (
  215.         "pushfq\n"
  216.         "popq %0\n"
  217.         : "=r" (v)
  218.     );
  219.     return v;
  220. }
  221.  
  222. /** Write to MSR */
  223. static inline void write_msr(uint32_t msr, uint64_t value)
  224. {
  225.     __asm__ volatile (
  226.         "wrmsr;" : : "c" (msr),
  227.         "a" ((uint32_t)(value)),
  228.         "d" ((uint32_t)(value >> 32))
  229.         );
  230. }
  231.  
  232. static inline unative_t read_msr(uint32_t msr)
  233. {
  234.     uint32_t ax, dx;
  235.  
  236.     __asm__ volatile (
  237.         "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)
  238.         );
  239.     return ((uint64_t)dx << 32) | ax;
  240. }
  241.  
  242.  
  243. /** Enable local APIC
  244.  *
  245.  * Enable local APIC in MSR.
  246.  */
  247. static inline void enable_l_apic_in_msr()
  248. {
  249.     __asm__ volatile (
  250.         "movl $0x1b, %%ecx\n"
  251.         "rdmsr\n"
  252.         "orl $(1<<11),%%eax\n"
  253.         "orl $(0xfee00000),%%eax\n"
  254.         "wrmsr\n"
  255.         :
  256.         :
  257.         :"%eax","%ecx","%edx"
  258.         );
  259. }
  260.  
  261. static inline uintptr_t * get_ip()
  262. {
  263.     uintptr_t *ip;
  264.  
  265.     __asm__ volatile (
  266.         "mov %%rip, %0"
  267.         : "=r" (ip)
  268.         );
  269.     return ip;
  270. }
  271.  
  272. /** Invalidate TLB Entry.
  273.  *
  274.  * @param addr Address on a page whose TLB entry is to be invalidated.
  275.  */
  276. static inline void invlpg(uintptr_t addr)
  277. {
  278.     __asm__ volatile ("invlpg %0\n" :: "m" (*((unative_t *)addr)));
  279. }
  280.  
  281. /** Load GDTR register from memory.
  282.  *
  283.  * @param gdtr_reg Address of memory from where to load GDTR.
  284.  */
  285. static inline void gdtr_load(struct ptr_16_64 *gdtr_reg)
  286. {
  287.     __asm__ volatile ("lgdtq %0\n" : : "m" (*gdtr_reg));
  288. }
  289.  
  290. /** Store GDTR register to memory.
  291.  *
  292.  * @param gdtr_reg Address of memory to where to load GDTR.
  293.  */
  294. static inline void gdtr_store(struct ptr_16_64 *gdtr_reg)
  295. {
  296.     __asm__ volatile ("sgdtq %0\n" : : "m" (*gdtr_reg));
  297. }
  298.  
  299. /** Load IDTR register from memory.
  300.  *
  301.  * @param idtr_reg Address of memory from where to load IDTR.
  302.  */
  303. static inline void idtr_load(struct ptr_16_64 *idtr_reg)
  304. {
  305.     __asm__ volatile ("lidtq %0\n" : : "m" (*idtr_reg));
  306. }
  307.  
  308. /** Load TR from descriptor table.
  309.  *
  310.  * @param sel Selector specifying descriptor of TSS segment.
  311.  */
  312. static inline void tr_load(uint16_t sel)
  313. {
  314.     __asm__ volatile ("ltr %0" : : "r" (sel));
  315. }
  316.  
  317. #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
  318.     { \
  319.     unative_t res; \
  320.     __asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \
  321.     return res; \
  322.     }
  323.  
  324. #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
  325.     { \
  326.     __asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \
  327.     }
  328.  
  329. GEN_READ_REG(cr0)
  330. GEN_READ_REG(cr2)
  331. GEN_READ_REG(cr3)
  332. GEN_WRITE_REG(cr3)
  333.  
  334. GEN_READ_REG(dr0)
  335. GEN_READ_REG(dr1)
  336. GEN_READ_REG(dr2)
  337. GEN_READ_REG(dr3)
  338. GEN_READ_REG(dr6)
  339. GEN_READ_REG(dr7)
  340.  
  341. GEN_WRITE_REG(dr0)
  342. GEN_WRITE_REG(dr1)
  343. GEN_WRITE_REG(dr2)
  344. GEN_WRITE_REG(dr3)
  345. GEN_WRITE_REG(dr6)
  346. GEN_WRITE_REG(dr7)
  347.  
  348. extern size_t interrupt_handler_size;
  349. extern void interrupt_handlers(void);
  350.  
  351. #endif
  352.  
  353. /** @}
  354.  */
  355.