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  1. /*
  2.  * Copyright (C) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #ifndef __amd64_ASM_H__
  30. #define __amd64_ASM_H__
  31.  
  32. #include <arch/types.h>
  33. #include <config.h>
  34.  
  35. extern void asm_delay_loop(__u32 t);
  36. extern void asm_fake_loop(__u32 t);
  37.  
  38. /** Return base address of current stack.
  39.  *
  40.  * Return the base address of the current stack.
  41.  * The stack is assumed to be STACK_SIZE bytes long.
  42.  * The stack must start on page boundary.
  43.  */
  44. static inline __address get_stack_base(void)
  45. {
  46.     __address v;
  47.    
  48.     __asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));
  49.    
  50.     return v;
  51. }
  52.  
  53. static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };
  54. static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };
  55.  
  56.  
  57. /** Byte from port
  58.  *
  59.  * Get byte from port
  60.  *
  61.  * @param port Port to read from
  62.  * @return Value read
  63.  */
  64. static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
  65.  
  66. /** Byte to port
  67.  *
  68.  * Output byte to port
  69.  *
  70.  * @param port Port to write to
  71.  * @param val Value to write
  72.  */
  73. static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
  74.  
  75. /** Enable interrupts.
  76.  *
  77.  * Enable interrupts and return previous
  78.  * value of EFLAGS.
  79.  *
  80.  * @return Old interrupt priority level.
  81.  */
  82. static inline ipl_t interrupts_enable(void) {
  83.     ipl_t v;
  84.     __asm__ volatile (
  85.         "pushfq\n"
  86.         "popq %0\n"
  87.         "sti\n"
  88.         : "=r" (v)
  89.     );
  90.     return v;
  91. }
  92.  
  93. /** Disable interrupts.
  94.  *
  95.  * Disable interrupts and return previous
  96.  * value of EFLAGS.
  97.  *
  98.  * @return Old interrupt priority level.
  99.  */
  100. static inline ipl_t interrupts_disable(void) {
  101.     ipl_t v;
  102.     __asm__ volatile (
  103.         "pushfq\n"
  104.         "popq %0\n"
  105.         "cli\n"
  106.         : "=r" (v)
  107.         );
  108.     return v;
  109. }
  110.  
  111. /** Restore interrupt priority level.
  112.  *
  113.  * Restore EFLAGS.
  114.  *
  115.  * @param ipl Saved interrupt priority level.
  116.  */
  117. static inline void interrupts_restore(ipl_t ipl) {
  118.     __asm__ volatile (
  119.         "pushq %0\n"
  120.         "popfq\n"
  121.         : : "r" (ipl)
  122.         );
  123. }
  124.  
  125. /** Return interrupt priority level.
  126.  *
  127.  * Return EFLAFS.
  128.  *
  129.  * @return Current interrupt priority level.
  130.  */
  131. static inline ipl_t interrupts_read(void) {
  132.     ipl_t v;
  133.     __asm__ volatile (
  134.         "pushfq\n"
  135.         "popq %0\n"
  136.         : "=r" (v)
  137.     );
  138.     return v;
  139. }
  140.  
  141. /** Read CR0
  142.  *
  143.  * Return value in CR0
  144.  *
  145.  * @return Value read.
  146.  */
  147. static inline __u64 read_cr0(void)
  148. {
  149.     __u64 v;
  150.     __asm__ volatile ("movq %%cr0,%0\n" : "=r" (v));
  151.     return v;
  152. }
  153.  
  154. /** Read CR2
  155.  *
  156.  * Return value in CR2
  157.  *
  158.  * @return Value read.
  159.  */
  160. static inline __u64 read_cr2(void)
  161. {
  162.     __u64 v;
  163.     __asm__ volatile ("movq %%cr2,%0\n" : "=r" (v));
  164.     return v;
  165. }
  166.  
  167. /** Write CR3
  168.  *
  169.  * Write value to CR3.
  170.  *
  171.  * @param v Value to be written.
  172.  */
  173. static inline void write_cr3(__u64 v)
  174. {
  175.     __asm__ volatile ("movq %0,%%cr3\n" : : "r" (v));
  176. }
  177.  
  178. /** Read CR3
  179.  *
  180.  * Return value in CR3
  181.  *
  182.  * @return Value read.
  183.  */
  184. static inline __u64 read_cr3(void)
  185. {
  186.     __u64 v;
  187.     __asm__ volatile ("movq %%cr3,%0" : "=r" (v));
  188.     return v;
  189. }
  190.  
  191. /** Write to MSR */
  192. static inline void write_msr(__u32 msr, __u64 value)
  193. {
  194.     __asm__ volatile (
  195.         "wrmsr;" : : "c" (msr),
  196.         "a" ((__u32)(value)),
  197.         "d" ((__u32)(value >> 32))
  198.         );
  199. }
  200.  
  201. static inline __native read_msr(__u32 msr)
  202. {
  203.     __u32 ax, dx;
  204.  
  205.     __asm__ volatile (
  206.         "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)
  207.         );
  208.     return ((__u64)dx << 32) | ax;
  209. }
  210.  
  211.  
  212. /** Enable local APIC
  213.  *
  214.  * Enable local APIC in MSR.
  215.  */
  216. static inline void enable_l_apic_in_msr()
  217. {
  218.     __asm__ volatile (
  219.         "movl $0x1b, %%ecx\n"
  220.         "rdmsr\n"
  221.         "orl $(1<<11),%%eax\n"
  222.         "orl $(0xfee00000),%%eax\n"
  223.         "wrmsr\n"
  224.         :
  225.         :
  226.         :"%eax","%ecx","%edx"
  227.         );
  228. }
  229.  
  230. static inline __address * get_ip()
  231. {
  232.     __address *ip;
  233.  
  234.     __asm__ volatile (
  235.         "mov %%rip, %0"
  236.         : "=r" (ip)
  237.         );
  238.     return ip;
  239. }
  240.  
  241. /** Invalidate TLB Entry.
  242.  *
  243.  * @param addr Address on a page whose TLB entry is to be invalidated.
  244.  */
  245. static inline void invlpg(__address addr)
  246. {
  247.         __asm__ volatile ("invlpg %0\n" :: "m" (addr));
  248. }
  249.  
  250. extern size_t interrupt_handler_size;
  251. extern void interrupt_handlers(void);
  252.  
  253. #endif
  254.