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  1. /*
  2.  * Copyright (c) 2006 Martin Decky
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup ia32xen
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #include <arch/pm.h>
  36. #include <config.h>
  37. #include <arch/types.h>
  38. #include <typedefs.h>
  39. #include <arch/interrupt.h>
  40. #include <arch/asm.h>
  41. #include <arch/context.h>
  42. #include <panic.h>
  43. #include <arch/mm/page.h>
  44. #include <mm/slab.h>
  45. #include <memstr.h>
  46. #include <arch/boot/boot.h>
  47. #include <interrupt.h>
  48.  
  49. /*
  50.  * Early ia32xen configuration functions and data structures.
  51.  */
  52.  
  53. /*
  54.  * We have no use for segmentation so we set up flat mode. In this
  55.  * mode, we use, for each privilege level, two segments spanning the
  56.  * whole memory. One is for code and one is for data.
  57.  *
  58.  * One is for GS register which holds pointer to the TLS thread
  59.  * structure in it's base.
  60.  */
  61. descriptor_t gdt[GDT_ITEMS] = {
  62.     /* NULL descriptor */
  63.     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
  64.     /* KTEXT descriptor */
  65.     { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
  66.     /* KDATA descriptor */
  67.     { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
  68.     /* UTEXT descriptor */
  69.     { 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
  70.     /* UDATA descriptor */
  71.     { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
  72.     /* TSS descriptor - set up will be completed later */
  73.     { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
  74.     /* TLS descriptor */
  75.     { 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
  76. };
  77.  
  78. static trap_info_t traps[IDT_ITEMS + 1];
  79.  
  80. static tss_t tss;
  81.  
  82. tss_t *tss_p = NULL;
  83.  
  84. /* gdtr is changed by kmp before next CPU is initialized */
  85. ptr_16_32_t bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((uintptr_t) gdt) };
  86. ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (uintptr_t) gdt };
  87.  
  88. void gdt_setbase(descriptor_t *d, uintptr_t base)
  89. {
  90.     d->base_0_15 = base & 0xffff;
  91.     d->base_16_23 = ((base) >> 16) & 0xff;
  92.     d->base_24_31 = ((base) >> 24) & 0xff;
  93. }
  94.  
  95. void gdt_setlimit(descriptor_t *d, uint32_t limit)
  96. {
  97.     d->limit_0_15 = limit & 0xffff;
  98.     d->limit_16_19 = (limit >> 16) & 0xf;
  99. }
  100.  
  101. void tss_initialize(tss_t *t)
  102. {
  103.     memsetb((uintptr_t) t, sizeof(struct tss), 0);
  104. }
  105.  
  106. static void trap(void)
  107. {
  108. }
  109.  
  110. void traps_init(void)
  111. {
  112.     index_t i;
  113.    
  114.     for (i = 0; i < IDT_ITEMS; i++) {
  115.         traps[i].vector = i;
  116.        
  117.         if (i == VECTOR_SYSCALL)
  118.             traps[i].flags = 3;
  119.         else
  120.             traps[i].flags = 0;
  121.        
  122.         traps[i].cs = XEN_CS;
  123.         traps[i].address = trap;
  124.     }
  125.     traps[IDT_ITEMS].vector = 0;
  126.     traps[IDT_ITEMS].flags = 0;
  127.     traps[IDT_ITEMS].cs = 0;
  128.     traps[IDT_ITEMS].address = NULL;
  129. }
  130.  
  131.  
  132. /* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
  133. static void clean_IOPL_NT_flags(void)
  134. {
  135. //  asm volatile (
  136. //      "pushfl\n"
  137. //      "pop %%eax\n"
  138. //      "and $0xffff8fff, %%eax\n"
  139. //      "push %%eax\n"
  140. //      "popfl\n"
  141. //      : : : "eax"
  142. //  );
  143. }
  144.  
  145. /* Clean AM(18) flag in CR0 register */
  146. static void clean_AM_flag(void)
  147. {
  148. //  asm volatile (
  149. //      "mov %%cr0, %%eax\n"
  150. //      "and $0xfffbffff, %%eax\n"
  151. //      "mov %%eax, %%cr0\n"
  152. //      : : : "eax"
  153. //  );
  154. }
  155.  
  156. void pm_init(void)
  157. {
  158.     descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
  159.  
  160. //  gdtr_load(&gdtr);
  161.    
  162.     if (config.cpu_active == 1) {
  163.         traps_init();
  164.         xen_set_trap_table(traps);
  165.         /*
  166.          * NOTE: bootstrap CPU has statically allocated TSS, because
  167.          * the heap hasn't been initialized so far.
  168.          */
  169.         tss_p = &tss;
  170.     } else {
  171.         tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
  172.         if (!tss_p)
  173.             panic("could not allocate TSS\n");
  174.     }
  175.  
  176. //  tss_initialize(tss_p);
  177.    
  178.     gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
  179.     gdt_p[TSS_DES].special = 1;
  180.     gdt_p[TSS_DES].granularity = 0;
  181.    
  182.     gdt_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
  183.     gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
  184.  
  185.     /*
  186.      * As of this moment, the current CPU has its own GDT pointing
  187.      * to its own TSS. We just need to load the TR register.
  188.      */
  189. //  tr_load(selector(TSS_DES));
  190.    
  191.     clean_IOPL_NT_flags();    /* Disable I/O on nonprivileged levels and clear NT flag. */
  192.     clean_AM_flag();          /* Disable alignment check */
  193. }
  194.  
  195. void set_tls_desc(uintptr_t tls)
  196. {
  197.     ptr_16_32_t cpugdtr;
  198.     descriptor_t *gdt_p;
  199.  
  200.     gdtr_store(&cpugdtr);
  201.     gdt_p = (descriptor_t *) cpugdtr.base;
  202.     gdt_setbase(&gdt_p[TLS_DES], tls);
  203.     /* Reload gdt register to update GS in CPU */
  204.     gdtr_load(&cpugdtr);
  205. }
  206.  
  207. /** @}
  208.  */
  209.