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  1. /*
  2.  * Copyright (C) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #ifndef __ia32_BARRIER_H__
  30. #define __ia32_BARRIER_H__
  31.  
  32. /*
  33.  * NOTE:
  34.  * No barriers for critical section (i.e. spinlock) on IA-32 are needed:
  35.  * - spinlock_lock() and spinlock_trylock() use serializing XCHG instruction
  36.  * - writes cannot pass reads on IA-32 => spinlock_unlock() needs no barriers
  37.  */
  38.  
  39. /*
  40.  * Provisions are made to prevent compiler from reordering instructions itself.
  41.  */
  42.  
  43. #define CS_ENTER_BARRIER()  __asm__ volatile ("" ::: "memory")
  44. #define CS_LEAVE_BARRIER()  __asm__ volatile ("" ::: "memory")
  45.  
  46. #ifdef CONFIG_FENCES_P4
  47. #   define memory_barrier() __asm__ volatile ("mfence\n" ::: "memory")
  48. #   define read_barrier()       __asm__ volatile ("lfence\n" ::: "memory")
  49. #   define write_barrier()      __asm__ volatile ("sfence\n" ::: "memory")
  50. #elif CONFIG_FENCES_P3
  51. #   define memory_barrier() __asm__ volatile ("\n" ::: "memory")
  52. #   define read_barrier()       __asm__ volatile ("\n" ::: "memory")
  53. #   define write_barrier()      __asm__ volatile ("sfence\n" ::: "memory")
  54. #endif
  55.  
  56. #endif
  57.