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  1. /*
  2.  * Copyright (C) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #include <arch/mm/tlb.h>
  30. #include <mm/tlb.h>
  31. #include <arch/mm/frame.h>
  32. #include <arch/mm/page.h>
  33. #include <arch/mm/mmu.h>
  34. #include <mm/asid.h>
  35. #include <print.h>
  36. #include <arch/types.h>
  37. #include <typedefs.h>
  38. #include <config.h>
  39. #include <arch/trap/trap.h>
  40. #include <panic.h>
  41. #include <arch/asm.h>
  42. #include <symtab.h>
  43.  
  44. #include <arch/drivers/fb.h>
  45. #include <arch/drivers/i8042.h>
  46.  
  47. char *context_encoding[] = {
  48.     "Primary",
  49.     "Secondary",
  50.     "Nucleus",
  51.     "Reserved"
  52. };
  53.  
  54. /** Initialize ITLB and DTLB.
  55.  *
  56.  * The goal of this function is to disable MMU
  57.  * so that both TLBs can be purged and new
  58.  * kernel 4M locked entry can be installed.
  59.  * After TLB is initialized, MMU is enabled
  60.  * again.
  61.  *
  62.  * Switching MMU off imposes the requirement for
  63.  * the kernel to run in identity mapped environment.
  64.  */
  65. void tlb_arch_init(void)
  66. {
  67.     tlb_tag_access_reg_t tag;
  68.     tlb_data_t data;
  69.     frame_address_t fr;
  70.     page_address_t pg;
  71.  
  72.     fr.address = config.base;
  73.     pg.address = config.base;
  74.  
  75.     immu_disable();
  76.     dmmu_disable();
  77.  
  78.     /*
  79.      * Demap everything, especially OpenFirmware.
  80.      */
  81.     itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
  82.     dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
  83.    
  84.     /*
  85.      * We do identity mapping of 4M-page at 4M.
  86.      */
  87.     tag.value = ASID_KERNEL;
  88.     tag.vpn = pg.vpn;
  89.  
  90.     itlb_tag_access_write(tag.value);
  91.     dtlb_tag_access_write(tag.value);
  92.  
  93.     data.value = 0;
  94.     data.v = true;
  95.     data.size = PAGESIZE_4M;
  96.     data.pfn = fr.pfn;
  97.     data.l = true;
  98.     data.cp = 1;
  99.     data.cv = 1;
  100.     data.p = true;
  101.     data.w = true;
  102.     data.g = true;
  103.  
  104.     itlb_data_in_write(data.value);
  105.     dtlb_data_in_write(data.value);
  106.  
  107.     /*
  108.      * Register window traps can occur before MMU is enabled again.
  109.      * This ensures that any such traps will be handled from
  110.      * kernel identity mapped trap handler.
  111.      */
  112.     trap_switch_trap_table();
  113.    
  114.     tlb_invalidate_all();
  115.  
  116.     dmmu_enable();
  117.     immu_enable();
  118. }
  119.  
  120. /** Insert privileged mapping into DMMU TLB.
  121.  *
  122.  * @param page Virtual page address.
  123.  * @param frame Physical frame address.
  124.  * @param pagesize Page size.
  125.  * @param locked True for permanent mappings, false otherwise.
  126.  * @param cacheable True if the mapping is cacheable, false otherwise.
  127.  */
  128. void dtlb_insert_mapping(__address page, __address frame, int pagesize, bool locked, bool cacheable)
  129. {
  130.     tlb_tag_access_reg_t tag;
  131.     tlb_data_t data;
  132.     page_address_t pg;
  133.     frame_address_t fr;
  134.  
  135.     pg.address = page;
  136.     fr.address = frame;
  137.  
  138.     tag.value = ASID_KERNEL;
  139.     tag.vpn = pg.vpn;
  140.  
  141.     dtlb_tag_access_write(tag.value);
  142.  
  143.     data.value = 0;
  144.     data.v = true;
  145.     data.size = pagesize;
  146.     data.pfn = fr.pfn;
  147.     data.l = locked;
  148.     data.cp = cacheable;
  149.     data.cv = cacheable;
  150.     data.p = true;
  151.     data.w = true;
  152.     data.g = true;
  153.  
  154.     dtlb_data_in_write(data.value);
  155. }
  156.  
  157. /** ITLB miss handler. */
  158. void fast_instruction_access_mmu_miss(void)
  159. {
  160.     panic("%s\n", __FUNCTION__);
  161. }
  162.  
  163. /** DTLB miss handler. */
  164. void fast_data_access_mmu_miss(void)
  165. {
  166.     tlb_tag_access_reg_t tag;
  167.     __address tpc;
  168.     char *tpc_str;
  169.  
  170.     tag.value = dtlb_tag_access_read();
  171.     if (tag.context != ASID_KERNEL || tag.vpn == 0) {
  172.         tpc = tpc_read();
  173.         tpc_str = get_symtab_entry(tpc);
  174.  
  175.         printf("Faulting page: %P, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context);
  176.         printf("TPC=%P, (%s)\n", tpc, tpc_str ? tpc_str : "?");
  177.         panic("%s\n", __FUNCTION__);
  178.     }
  179.  
  180.     /*
  181.      * Identity map piece of faulting kernel address space.
  182.      */
  183.     dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true);
  184. }
  185.  
  186. /** DTLB protection fault handler. */
  187. void fast_data_access_protection(void)
  188. {
  189.     panic("%s\n", __FUNCTION__);
  190. }
  191.  
  192. /** Print contents of both TLBs. */
  193. void tlb_print(void)
  194. {
  195.     int i;
  196.     tlb_data_t d;
  197.     tlb_tag_read_reg_t t;
  198.    
  199.     printf("I-TLB contents:\n");
  200.     for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
  201.         d.value = itlb_data_access_read(i);
  202.         t.value = itlb_tag_read_read(i);
  203.        
  204.         printf("%d: vpn=%#llX, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#X, diag=%#X, pfn=%#X, soft=%#X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
  205.             i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
  206.     }
  207.  
  208.     printf("D-TLB contents:\n");
  209.     for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
  210.         d.value = dtlb_data_access_read(i);
  211.         t.value = dtlb_tag_read_read(i);
  212.        
  213.         printf("%d: vpn=%#llX, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#X, diag=%#X, pfn=%#X, soft=%#X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
  214.             i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
  215.     }
  216.  
  217. }
  218.  
  219. /** Invalidate all unlocked ITLB and DTLB entries. */
  220. void tlb_invalidate_all(void)
  221. {
  222.     int i;
  223.     tlb_data_t d;
  224.     tlb_tag_read_reg_t t;
  225.  
  226.     for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
  227.         d.value = itlb_data_access_read(i);
  228.         if (!d.l) {
  229.             t.value = itlb_tag_read_read(i);
  230.             d.v = false;
  231.             itlb_tag_access_write(t.value);
  232.             itlb_data_access_write(i, d.value);
  233.         }
  234.     }
  235.    
  236.     for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
  237.         d.value = dtlb_data_access_read(i);
  238.         if (!d.l) {
  239.             t.value = dtlb_tag_read_read(i);
  240.             d.v = false;
  241.             dtlb_tag_access_write(t.value);
  242.             dtlb_data_access_write(i, d.value);
  243.         }
  244.     }
  245.    
  246. }
  247.  
  248. /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
  249.  *
  250.  * @param asid Address Space ID.
  251.  */
  252. void tlb_invalidate_asid(asid_t asid)
  253. {
  254.     /* TODO: write asid to some Context register and encode the register in second parameter below. */
  255.     itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
  256.     dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
  257. }
  258.  
  259. /** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
  260.  *
  261.  * @param asid Address Space ID.
  262.  * @param page First page which to sweep out from ITLB and DTLB.
  263.  * @param cnt Number of ITLB and DTLB entries to invalidate.
  264.  */
  265. void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
  266. {
  267.     int i;
  268.    
  269.     for (i = 0; i < cnt; i++) {
  270.         /* TODO: write asid to some Context register and encode the register in second parameter below. */
  271.         itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
  272.         dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
  273.     }
  274. }
  275.