Subversion Repositories HelenOS-historic

Rev

Rev 873 | Rev 901 | Go to most recent revision | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed

  1. /*
  2.  * Copyright (C) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #ifndef __sparc64_TLB_H__
  30. #define __sparc64_TLB_H__
  31.  
  32. #include <arch/mm/tte.h>
  33. #include <arch/mm/mmu.h>
  34. #include <arch/mm/page.h>
  35. #include <arch/asm.h>
  36. #include <arch/barrier.h>
  37. #include <arch/types.h>
  38. #include <typedefs.h>
  39.  
  40. #define ITLB_ENTRY_COUNT        64
  41. #define DTLB_ENTRY_COUNT        64
  42.  
  43. /** Page sizes. */
  44. #define PAGESIZE_8K 0
  45. #define PAGESIZE_64K    1
  46. #define PAGESIZE_512K   2
  47. #define PAGESIZE_4M 3
  48.  
  49. union tlb_context_reg {
  50.     __u64 v;
  51.     struct {
  52.         unsigned long : 51;
  53.         unsigned context : 13;      /**< Context/ASID. */
  54.     } __attribute__ ((packed));
  55. };
  56. typedef union tlb_context_reg tlb_context_reg_t;
  57.  
  58. /** I-/D-TLB Data In/Access Register type. */
  59. typedef tte_data_t tlb_data_t;
  60.  
  61. /** I-/D-TLB Data Access Address in Alternate Space. */
  62. union tlb_data_access_addr {
  63.     __u64 value;
  64.     struct {
  65.         __u64 : 55;
  66.         unsigned tlb_entry : 6;
  67.         unsigned : 3;
  68.     } __attribute__ ((packed));
  69. };
  70. typedef union tlb_data_access_addr tlb_data_access_addr_t;
  71. typedef union tlb_data_access_addr tlb_tag_read_addr_t;
  72.  
  73. /** I-/D-TLB Tag Read Register. */
  74. union tlb_tag_read_reg {
  75.     __u64 value;
  76.     struct {
  77.         __u64 vpn : 51;     /**< Virtual Address bits 63:13. */
  78.         unsigned context : 13;  /**< Context identifier. */
  79.     } __attribute__ ((packed));
  80. };
  81. typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
  82. typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
  83.  
  84. /** TLB Demap Operation types. */
  85. #define TLB_DEMAP_PAGE      0
  86. #define TLB_DEMAP_CONTEXT   1
  87.  
  88. /** TLB Demap Operation Context register encodings. */
  89. #define TLB_DEMAP_PRIMARY   0
  90. #define TLB_DEMAP_SECONDARY 1
  91. #define TLB_DEMAP_NUCLEUS   2
  92.  
  93. /** TLB Demap Operation Address. */
  94. union tlb_demap_addr {
  95.     __u64 value;
  96.     struct {
  97.         __u64 vpn: 51;      /**< Virtual Address bits 63:13. */
  98.         unsigned : 6;       /**< Ignored. */
  99.         unsigned type : 1;  /**< The type of demap operation. */
  100.         unsigned context : 2;   /**< Context register selection. */
  101.         unsigned : 4;       /**< Zero. */
  102.     } __attribute__ ((packed));
  103. };
  104. typedef union tlb_demap_addr tlb_demap_addr_t;
  105.  
  106. /** TLB Synchronous Fault Status Register. */
  107. union tlb_sfsr_reg {
  108.     __u64 value;
  109.     struct {
  110.         unsigned long : 39; /**< Implementation dependent. */
  111.         unsigned nf : 1;    /**< Nonfaulting load. */
  112.         unsigned asi : 8;   /**< ASI. */
  113.         unsigned tm : 1;    /**< TLB miss. */
  114.         unsigned : 1;
  115.         unsigned ft : 7;    /**< Fault type. */
  116.         unsigned e : 1;     /**< Side-effect bit. */
  117.         unsigned ct : 2;    /**< Context Register selection. */
  118.         unsigned pr : 1;    /**< Privilege bit. */
  119.         unsigned w : 1;     /**< Write bit. */
  120.         unsigned ow : 1;    /**< Overwrite bit. */
  121.         unsigned fv : 1;    /**< Fault Valid bit. */
  122.     } __attribute__ ((packed));
  123. };
  124. typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
  125.  
  126. /** Read MMU Primary Context Register.
  127.  *
  128.  * @return Current value of Primary Context Register.
  129.  */
  130. static inline __u64 mmu_primary_context_read(void)
  131. {
  132.     return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
  133. }
  134.  
  135. /** Write MMU Primary Context Register.
  136.  *
  137.  * @param v New value of Primary Context Register.
  138.  */
  139. static inline void mmu_primary_context_write(__u64 v)
  140. {
  141.     asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
  142.     flush();
  143. }
  144.  
  145. /** Read MMU Secondary Context Register.
  146.  *
  147.  * @return Current value of Secondary Context Register.
  148.  */
  149. static inline __u64 mmu_secondary_context_read(void)
  150. {
  151.     return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
  152. }
  153.  
  154. /** Write MMU Primary Context Register.
  155.  *
  156.  * @param v New value of Primary Context Register.
  157.  */
  158. static inline void mmu_secondary_context_write(__u64 v)
  159. {
  160.     asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
  161.     flush();
  162. }
  163.  
  164. /** Read IMMU TLB Data Access Register.
  165.  *
  166.  * @param entry TLB Entry index.
  167.  *
  168.  * @return Current value of specified IMMU TLB Data Access Register.
  169.  */
  170. static inline __u64 itlb_data_access_read(index_t entry)
  171. {
  172.     tlb_data_access_addr_t reg;
  173.    
  174.     reg.value = 0;
  175.     reg.tlb_entry = entry;
  176.     return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
  177. }
  178.  
  179. /** Write IMMU TLB Data Access Register.
  180.  *
  181.  * @param entry TLB Entry index.
  182.  * @param value Value to be written.
  183.  */
  184. static inline void itlb_data_access_write(index_t entry, __u64 value)
  185. {
  186.     tlb_data_access_addr_t reg;
  187.    
  188.     reg.value = 0;
  189.     reg.tlb_entry = entry;
  190.     asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
  191.     flush();
  192. }
  193.  
  194. /** Read DMMU TLB Data Access Register.
  195.  *
  196.  * @param entry TLB Entry index.
  197.  *
  198.  * @return Current value of specified DMMU TLB Data Access Register.
  199.  */
  200. static inline __u64 dtlb_data_access_read(index_t entry)
  201. {
  202.     tlb_data_access_addr_t reg;
  203.    
  204.     reg.value = 0;
  205.     reg.tlb_entry = entry;
  206.     return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
  207. }
  208.  
  209. /** Write DMMU TLB Data Access Register.
  210.  *
  211.  * @param entry TLB Entry index.
  212.  * @param value Value to be written.
  213.  */
  214. static inline void dtlb_data_access_write(index_t entry, __u64 value)
  215. {
  216.     tlb_data_access_addr_t reg;
  217.    
  218.     reg.value = 0;
  219.     reg.tlb_entry = entry;
  220.     asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
  221.     flush();
  222. }
  223.  
  224. /** Read IMMU TLB Tag Read Register.
  225.  *
  226.  * @param entry TLB Entry index.
  227.  *
  228.  * @return Current value of specified IMMU TLB Tag Read Register.
  229.  */
  230. static inline __u64 itlb_tag_read_read(index_t entry)
  231. {
  232.     tlb_tag_read_addr_t tag;
  233.  
  234.     tag.value = 0;
  235.     tag.tlb_entry = entry;
  236.     return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
  237. }
  238.  
  239. /** Read DMMU TLB Tag Read Register.
  240.  *
  241.  * @param entry TLB Entry index.
  242.  *
  243.  * @return Current value of specified DMMU TLB Tag Read Register.
  244.  */
  245. static inline __u64 dtlb_tag_read_read(index_t entry)
  246. {
  247.     tlb_tag_read_addr_t tag;
  248.  
  249.     tag.value = 0;
  250.     tag.tlb_entry = entry;
  251.     return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
  252. }
  253.  
  254. /** Write IMMU TLB Tag Access Register.
  255.  *
  256.  * @param v Value to be written.
  257.  */
  258. static inline void itlb_tag_access_write(__u64 v)
  259. {
  260.     asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
  261.     flush();
  262. }
  263.  
  264. /** Read IMMU TLB Tag Access Register.
  265.  *
  266.  * @return Current value of IMMU TLB Tag Access Register.
  267.  */
  268. static inline __u64 itlb_tag_access_read(void)
  269. {
  270.     return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
  271. }
  272.  
  273. /** Write DMMU TLB Tag Access Register.
  274.  *
  275.  * @param v Value to be written.
  276.  */
  277. static inline void dtlb_tag_access_write(__u64 v)
  278. {
  279.     asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
  280.     flush();
  281. }
  282.  
  283. /** Read DMMU TLB Tag Access Register.
  284.  *
  285.  * @return Current value of DMMU TLB Tag Access Register.
  286.  */
  287. static inline __u64 dtlb_tag_access_read(void)
  288. {
  289.     return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
  290. }
  291.  
  292.  
  293. /** Write IMMU TLB Data in Register.
  294.  *
  295.  * @param v Value to be written.
  296.  */
  297. static inline void itlb_data_in_write(__u64 v)
  298. {
  299.     asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
  300.     flush();
  301. }
  302.  
  303. /** Write DMMU TLB Data in Register.
  304.  *
  305.  * @param v Value to be written.
  306.  */
  307. static inline void dtlb_data_in_write(__u64 v)
  308. {
  309.     asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
  310.     flush();
  311. }
  312.  
  313. /** Read ITLB Synchronous Fault Status Register.
  314.  *
  315.  * @return Current content of I-SFSR register.
  316.  */
  317. static inline __u64 itlb_sfsr_read(void)
  318. {
  319.     return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
  320. }
  321.  
  322. /** Write ITLB Synchronous Fault Status Register.
  323.  *
  324.  * @param v New value of I-SFSR register.
  325.  */
  326. static inline void itlb_sfsr_write(__u64 v)
  327. {
  328.     asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
  329.     flush();
  330. }
  331.  
  332. /** Read DTLB Synchronous Fault Status Register.
  333.  *
  334.  * @return Current content of D-SFSR register.
  335.  */
  336. static inline __u64 dtlb_sfsr_read(void)
  337. {
  338.     return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
  339. }
  340.  
  341. /** Write DTLB Synchronous Fault Status Register.
  342.  *
  343.  * @param v New value of D-SFSR register.
  344.  */
  345. static inline void dtlb_sfsr_write(__u64 v)
  346. {
  347.     asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
  348.     flush();
  349. }
  350.  
  351. /** Read DTLB Synchronous Fault Address Register.
  352.  *
  353.  * @return Current content of D-SFAR register.
  354.  */
  355. static inline __u64 dtlb_sfar_read(void)
  356. {
  357.     return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
  358. }
  359.  
  360. /** Perform IMMU TLB Demap Operation.
  361.  *
  362.  * @param type Selects between context and page demap.
  363.  * @param context_encoding Specifies which Context register has Context ID for demap.
  364.  * @param page Address which is on the page to be demapped.
  365.  */
  366. static inline void itlb_demap(int type, int context_encoding, __address page)
  367. {
  368.     tlb_demap_addr_t da;
  369.     page_address_t pg;
  370.    
  371.     da.value = 0;
  372.     pg.address = page;
  373.    
  374.     da.type = type;
  375.     da.context = context_encoding;
  376.     da.vpn = pg.vpn;
  377.    
  378.     asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
  379.     flush();
  380. }
  381.  
  382. /** Perform DMMU TLB Demap Operation.
  383.  *
  384.  * @param type Selects between context and page demap.
  385.  * @param context_encoding Specifies which Context register has Context ID for demap.
  386.  * @param page Address which is on the page to be demapped.
  387.  */
  388. static inline void dtlb_demap(int type, int context_encoding, __address page)
  389. {
  390.     tlb_demap_addr_t da;
  391.     page_address_t pg;
  392.    
  393.     da.value = 0;
  394.     pg.address = page;
  395.    
  396.     da.type = type;
  397.     da.context = context_encoding;
  398.     da.vpn = pg.vpn;
  399.    
  400.     asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
  401.     flush();
  402. }
  403.  
  404. extern void fast_instruction_access_mmu_miss(void);
  405. extern void fast_data_access_mmu_miss(void);
  406. extern void fast_data_access_protection(void);
  407.  
  408. #endif
  409.