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  1. /*
  2.  * Copyright (C) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #ifndef __sparc64_ASM_H__
  30. #define __sparc64_ASM_H__
  31.  
  32. #include <typedefs.h>
  33. #include <arch/types.h>
  34. #include <arch/register.h>
  35. #include <config.h>
  36.  
  37. /** Read Processor State register.
  38.  *
  39.  * @return Value of PSTATE register.
  40.  */
  41. static inline __u64 pstate_read(void)
  42. {
  43.     __u64 v;
  44.    
  45.     __asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v));
  46.    
  47.     return v;
  48. }
  49.  
  50. /** Write Processor State register.
  51.  *
  52.  * @param New value of PSTATE register.
  53.  */
  54. static inline void pstate_write(__u64 v)
  55. {
  56.     __asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
  57. }
  58.  
  59.  
  60. /** Enable interrupts.
  61.  *
  62.  * Enable interrupts and return previous
  63.  * value of IPL.
  64.  *
  65.  * @return Old interrupt priority level.
  66.  */
  67. static inline ipl_t interrupts_enable(void) {
  68.     pstate_reg_t pstate;
  69.     __u64 value;
  70.    
  71.     value = pstate_read();
  72.     pstate.value = value;
  73.     pstate.ie = true;
  74.     pstate_write(pstate.value);
  75.    
  76.     return (ipl_t) value;
  77. }
  78.  
  79. /** Disable interrupts.
  80.  *
  81.  * Disable interrupts and return previous
  82.  * value of IPL.
  83.  *
  84.  * @return Old interrupt priority level.
  85.  */
  86. static inline ipl_t interrupts_disable(void) {
  87.     pstate_reg_t pstate;
  88.     __u64 value;
  89.    
  90.     value = pstate_read();
  91.     pstate.value = value;
  92.     pstate.ie = false;
  93.     pstate_write(pstate.value);
  94.    
  95.     return (ipl_t) value;
  96. }
  97.  
  98. /** Restore interrupt priority level.
  99.  *
  100.  * Restore IPL.
  101.  *
  102.  * @param ipl Saved interrupt priority level.
  103.  */
  104. static inline void interrupts_restore(ipl_t ipl) {
  105.     pstate_reg_t pstate;
  106.    
  107.     pstate.value = pstate_read();
  108.     pstate.ie = ((pstate_reg_t) ipl).ie;
  109.     pstate_write(pstate.value);
  110. }
  111.  
  112. /** Return interrupt priority level.
  113.  *
  114.  * Return IPL.
  115.  *
  116.  * @return Current interrupt priority level.
  117.  */
  118. static inline ipl_t interrupts_read(void) {
  119.     return (ipl_t) pstate_read();
  120. }
  121.  
  122. /** Return base address of current stack.
  123.  *
  124.  * Return the base address of the current stack.
  125.  * The stack is assumed to be STACK_SIZE bytes long.
  126.  * The stack must start on page boundary.
  127.  */
  128. static inline __address get_stack_base(void)
  129. {
  130.     __address v;
  131.    
  132.     __asm__ volatile ("and %%sp, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
  133.    
  134.     return v;
  135. }
  136.  
  137. /** Read Version Register.
  138.  *
  139.  * @return Value of VER register.
  140.  */
  141. static inline __u64 ver_read(void)
  142. {
  143.     __u64 v;
  144.    
  145.     __asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v));
  146.    
  147.     return v;
  148. }
  149.  
  150. /** Read Trap Base Address register.
  151.  *
  152.  * @return Current value in TBA.
  153.  */
  154. static inline __u64 tba_read(void)
  155. {
  156.     __u64 v;
  157.    
  158.     __asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v));
  159.    
  160.     return v;
  161. }
  162.  
  163. /** Write Trap Base Address register.
  164.  *
  165.  * @param New value of TBA.
  166.  */
  167. static inline void tba_write(__u64 v)
  168. {
  169.     __asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
  170. }
  171.  
  172. /** Load __u64 from alternate space.
  173.  *
  174.  * @param asi ASI determining the alternate space.
  175.  * @param va Virtual address within the ASI.
  176.  *
  177.  * @return Value read from the virtual address in the specified address space.
  178.  */
  179. static inline __u64 asi_u64_read(asi_t asi, __address va)
  180. {
  181.     __u64 v;
  182.    
  183.     __asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" (asi));
  184.    
  185.     return v;
  186. }
  187.  
  188. /** Store __u64 to alternate space.
  189.  *
  190.  * @param asi ASI determining the alternate space.
  191.  * @param va Virtual address within the ASI.
  192.  * @param v Value to be written.
  193.  */
  194. static inline void asi_u64_write(asi_t asi, __address va, __u64 v)
  195. {
  196.     __asm__ volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" (asi) : "memory");
  197. }
  198.  
  199. void cpu_halt(void);
  200. void cpu_sleep(void);
  201. void asm_delay_loop(__u32 t);
  202.  
  203. #endif
  204.