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  1. /*
  2.  * Copyright (C) 2001-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #include <arch/types.h>
  30. #include <arch/smp/apic.h>
  31. #include <arch/smp/ap.h>
  32. #include <arch/smp/mps.h>
  33. #include <arch/boot/boot.h>
  34. #include <mm/page.h>
  35. #include <time/delay.h>
  36. #include <interrupt.h>
  37. #include <arch/interrupt.h>
  38. #include <print.h>
  39. #include <arch/asm.h>
  40. #include <arch.h>
  41.  
  42. #ifdef CONFIG_SMP
  43.  
  44. /*
  45.  * Advanced Programmable Interrupt Controller for SMP systems.
  46.  * Tested on:
  47.  *  Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
  48.  *  Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
  49.  *  VMware Workstation 5.5 with 2 CPUs
  50.  *  QEMU 0.8.0 with 2-15 CPUs
  51.  *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
  52.  *  ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
  53.  *  MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
  54.  */
  55.  
  56. /*
  57.  * These variables either stay configured as initilalized, or are changed by
  58.  * the MP configuration code.
  59.  *
  60.  * Pay special attention to the volatile keyword. Without it, gcc -O2 would
  61.  * optimize the code too much and accesses to l_apic and io_apic, that must
  62.  * always be 32-bit, would use byte oriented instructions.
  63.  */
  64. volatile __u32 *l_apic = (__u32 *) 0xfee00000;
  65. volatile __u32 *io_apic = (__u32 *) 0xfec00000;
  66.  
  67. __u32 apic_id_mask = 0;
  68.  
  69. static int apic_poll_errors(void);
  70.  
  71. #ifdef LAPIC_VERBOSE
  72. static char *delmod_str[] = {
  73.     "Fixed",
  74.     "Lowest Priority",
  75.     "SMI",
  76.     "Reserved",
  77.     "NMI",
  78.     "INIT",
  79.     "STARTUP",
  80.     "ExtInt"
  81. };
  82.  
  83. static char *destmod_str[] = {
  84.     "Physical",
  85.     "Logical"
  86. };
  87.  
  88. static char *trigmod_str[] = {
  89.     "Edge",
  90.     "Level"
  91. };
  92.  
  93. static char *mask_str[] = {
  94.     "Unmasked",
  95.     "Masked"
  96. };
  97.  
  98. static char *delivs_str[] = {
  99.     "Idle",
  100.     "Send Pending"
  101. };
  102.  
  103. static char *tm_mode_str[] = {
  104.     "One-shot",
  105.     "Periodic"
  106. };
  107.  
  108. static char *intpol_str[] = {
  109.     "Polarity High",
  110.     "Polarity Low"
  111. };
  112. #endif /* LAPIC_VERBOSE */
  113.  
  114.  
  115. static void apic_spurious(int n, istate_t *istate);
  116. static void l_apic_timer_interrupt(int n, istate_t *istate);
  117.  
  118. /** Initialize APIC on BSP. */
  119. void apic_init(void)
  120. {
  121.     io_apic_id_t idreg;
  122.     int i;
  123.  
  124.     exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious);
  125.  
  126.     enable_irqs_function = io_apic_enable_irqs;
  127.     disable_irqs_function = io_apic_disable_irqs;
  128.     eoi_function = l_apic_eoi;
  129.    
  130.     /*
  131.      * Configure interrupt routing.
  132.      * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
  133.      * Other interrupts will be forwarded to the lowest priority CPU.
  134.      */
  135.     io_apic_disable_irqs(0xffff);
  136.     exc_register(VECTOR_CLK, "l_apic_timer", (iroutine) l_apic_timer_interrupt);
  137.     for (i = 0; i < IRQ_COUNT; i++) {
  138.         int pin;
  139.    
  140.         if ((pin = smp_irq_to_pin(i)) != -1) {
  141.             io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);
  142.         }
  143.     }
  144.    
  145.     /*
  146.      * Ensure that io_apic has unique ID.
  147.      */
  148.     idreg.value = io_apic_read(IOAPICID);
  149.     if ((1<<idreg.apic_id) & apic_id_mask) {    /* see if IO APIC ID is used already */
  150.         for (i = 0; i < APIC_ID_COUNT; i++) {
  151.             if (!((1<<i) & apic_id_mask)) {
  152.                 idreg.apic_id = i;
  153.                 io_apic_write(IOAPICID, idreg.value);
  154.                 break;
  155.             }
  156.         }
  157.     }
  158.  
  159.     /*
  160.      * Configure the BSP's lapic.
  161.      */
  162.     l_apic_init();
  163.  
  164.     l_apic_debug();
  165. }
  166.  
  167. /** APIC spurious interrupt handler.
  168.  *
  169.  * @param n Interrupt vector.
  170.  * @param stack Interrupted stack.
  171.  */
  172. void apic_spurious(int n, istate_t *istate)
  173. {
  174.     printf("cpu%d: APIC spurious interrupt\n", CPU->id);
  175. }
  176.  
  177. /** Poll for APIC errors.
  178.  *
  179.  * Examine Error Status Register and report all errors found.
  180.  *
  181.  * @return 0 on error, 1 on success.
  182.  */
  183. int apic_poll_errors(void)
  184. {
  185.     esr_t esr;
  186.    
  187.     esr.value = l_apic[ESR];
  188.    
  189.     if (esr.send_checksum_error)
  190.         printf("Send Checksum Error\n");
  191.     if (esr.receive_checksum_error)
  192.         printf("Receive Checksum Error\n");
  193.     if (esr.send_accept_error)
  194.         printf("Send Accept Error\n");
  195.     if (esr.receive_accept_error)
  196.         printf("Receive Accept Error\n");
  197.     if (esr.send_illegal_vector)
  198.         printf("Send Illegal Vector\n");
  199.     if (esr.received_illegal_vector)
  200.         printf("Received Illegal Vector\n");
  201.     if (esr.illegal_register_address)
  202.         printf("Illegal Register Address\n");
  203.  
  204.     return !esr.err_bitmap;
  205. }
  206.  
  207. /** Send all CPUs excluding CPU IPI vector.
  208.  *
  209.  * @param vector Interrupt vector to be sent.
  210.  *
  211.  * @return 0 on failure, 1 on success.
  212.  */
  213. int l_apic_broadcast_custom_ipi(__u8 vector)
  214. {
  215.     icr_t icr;
  216.  
  217.     icr.lo = l_apic[ICRlo];
  218.     icr.delmod = DELMOD_FIXED;
  219.     icr.destmod = DESTMOD_LOGIC;
  220.     icr.level = LEVEL_ASSERT;
  221.     icr.shorthand = SHORTHAND_ALL_EXCL;
  222.     icr.trigger_mode = TRIGMOD_LEVEL;
  223.     icr.vector = vector;
  224.  
  225.     l_apic[ICRlo] = icr.lo;
  226.  
  227.     icr.lo = l_apic[ICRlo];
  228.     if (icr.delivs == DELIVS_PENDING)
  229.         printf("IPI is pending.\n");
  230.  
  231.     return apic_poll_errors();
  232. }
  233.  
  234. /** Universal Start-up Algorithm for bringing up the AP processors.
  235.  *
  236.  * @param apicid APIC ID of the processor to be brought up.
  237.  *
  238.  * @return 0 on failure, 1 on success.
  239.  */
  240. int l_apic_send_init_ipi(__u8 apicid)
  241. {
  242.     icr_t icr;
  243.     int i;
  244.  
  245.     /*
  246.      * Read the ICR register in and zero all non-reserved fields.
  247.      */
  248.     icr.lo = l_apic[ICRlo];
  249.     icr.hi = l_apic[ICRhi];
  250.    
  251.     icr.delmod = DELMOD_INIT;
  252.     icr.destmod = DESTMOD_PHYS;
  253.     icr.level = LEVEL_ASSERT;
  254.     icr.trigger_mode = TRIGMOD_LEVEL;
  255.     icr.shorthand = SHORTHAND_NONE;
  256.     icr.vector = 0;
  257.     icr.dest = apicid;
  258.    
  259.     l_apic[ICRhi] = icr.hi;
  260.     l_apic[ICRlo] = icr.lo;
  261.  
  262.     /*
  263.      * According to MP Specification, 20us should be enough to
  264.      * deliver the IPI.
  265.      */
  266.     delay(20);
  267.  
  268.     if (!apic_poll_errors()) return 0;
  269.  
  270.     icr.lo = l_apic[ICRlo];
  271.     if (icr.delivs == DELIVS_PENDING)
  272.         printf("IPI is pending.\n");
  273.  
  274.     icr.delmod = DELMOD_INIT;
  275.     icr.destmod = DESTMOD_PHYS;
  276.     icr.level = LEVEL_DEASSERT;
  277.     icr.shorthand = SHORTHAND_NONE;
  278.     icr.trigger_mode = TRIGMOD_LEVEL;
  279.     icr.vector = 0;
  280.     l_apic[ICRlo] = icr.lo;
  281.  
  282.     /*
  283.      * Wait 10ms as MP Specification specifies.
  284.      */
  285.     delay(10000);
  286.  
  287.     if (!is_82489DX_apic(l_apic[LAVR])) {
  288.         /*
  289.          * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
  290.          */
  291.         for (i = 0; i<2; i++) {
  292.             icr.lo = l_apic[ICRlo];
  293.             icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */
  294.             icr.delmod = DELMOD_STARTUP;
  295.             icr.destmod = DESTMOD_PHYS;
  296.             icr.level = LEVEL_ASSERT;
  297.             icr.shorthand = SHORTHAND_NONE;
  298.             icr.trigger_mode = TRIGMOD_LEVEL;
  299.             l_apic[ICRlo] = icr.lo;
  300.             delay(200);
  301.         }
  302.     }
  303.    
  304.     return apic_poll_errors();
  305. }
  306.  
  307. /** Initialize Local APIC. */
  308. void l_apic_init(void)
  309. {
  310.     lvt_error_t error;
  311.     lvt_lint_t lint;
  312.     tpr_t tpr;
  313.     svr_t svr;
  314.     icr_t icr;
  315.     tdcr_t tdcr;
  316.     lvt_tm_t tm;
  317.     ldr_t ldr;
  318.     dfr_t dfr;
  319.     __u32 t1, t2;
  320.  
  321.     /* Initialize LVT Error register. */
  322.     error.value = l_apic[LVT_Err];
  323.     error.masked = true;
  324.     l_apic[LVT_Err] = error.value;
  325.  
  326.     /* Initialize LVT LINT0 register. */
  327.     lint.value = l_apic[LVT_LINT0];
  328.     lint.masked = true;
  329.     l_apic[LVT_LINT0] = lint.value;
  330.  
  331.     /* Initialize LVT LINT1 register. */
  332.     lint.value = l_apic[LVT_LINT1];
  333.     lint.masked = true;
  334.     l_apic[LVT_LINT1] = lint.value;
  335.  
  336.     /* Task Priority Register initialization. */
  337.     tpr.value = l_apic[TPR];
  338.     tpr.pri_sc = 0;
  339.     tpr.pri = 0;
  340.     l_apic[TPR] = tpr.value;
  341.    
  342.     /* Spurious-Interrupt Vector Register initialization. */
  343.     svr.value = l_apic[SVR];
  344.     svr.vector = VECTOR_APIC_SPUR;
  345.     svr.lapic_enabled = true;
  346.     svr.focus_checking = true;
  347.     l_apic[SVR] = svr.value;
  348.  
  349.     if (CPU->arch.family >= 6)
  350.         enable_l_apic_in_msr();
  351.    
  352.     /* Interrupt Command Register initialization. */
  353.     icr.lo = l_apic[ICRlo];
  354.     icr.delmod = DELMOD_INIT;
  355.     icr.destmod = DESTMOD_PHYS;
  356.     icr.level = LEVEL_DEASSERT;
  357.     icr.shorthand = SHORTHAND_ALL_INCL;
  358.     icr.trigger_mode = TRIGMOD_LEVEL;
  359.     l_apic[ICRlo] = icr.lo;
  360.    
  361.     /* Timer Divide Configuration Register initialization. */
  362.     tdcr.value = l_apic[TDCR];
  363.     tdcr.div_value = DIVIDE_1;
  364.     l_apic[TDCR] = tdcr.value;
  365.  
  366.     /* Program local timer. */
  367.     tm.value = l_apic[LVT_Tm];
  368.     tm.vector = VECTOR_CLK;
  369.     tm.mode = TIMER_PERIODIC;
  370.     tm.masked = false;
  371.     l_apic[LVT_Tm] = tm.value;
  372.  
  373.     /* Measure and configure the timer to generate timer interrupt each ms. */
  374.     t1 = l_apic[CCRT];
  375.     l_apic[ICRT] = 0xffffffff;
  376.  
  377.     while (l_apic[CCRT] == t1)
  378.         ;
  379.        
  380.     t1 = l_apic[CCRT];
  381.     delay(1000);
  382.     t2 = l_apic[CCRT];
  383.    
  384.     l_apic[ICRT] = t1-t2;
  385.    
  386.     /* Program Logical Destination Register. */
  387.     ldr.value = l_apic[LDR];
  388.     if (CPU->id < sizeof(CPU->id)*8)    /* size in bits */
  389.         ldr.id = (1<<CPU->id);
  390.     l_apic[LDR] = ldr.value;
  391.    
  392.     /* Program Destination Format Register for Flat mode. */
  393.     dfr.value = l_apic[DFR];
  394.     dfr.model = MODEL_FLAT;
  395.     l_apic[DFR] = dfr.value;
  396. }
  397.  
  398. /** Local APIC End of Interrupt. */
  399. void l_apic_eoi(void)
  400. {
  401.     l_apic[EOI] = 0;
  402. }
  403.  
  404. /** Dump content of Local APIC registers. */
  405. void l_apic_debug(void)
  406. {
  407. #ifdef LAPIC_VERBOSE
  408.     lvt_tm_t tm;
  409.     lvt_lint_t lint;
  410.     lvt_error_t error; 
  411.    
  412.     printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
  413.  
  414.     tm.value = l_apic[LVT_Tm];
  415.     printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
  416.     lint.value = l_apic[LVT_LINT0];
  417.     printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
  418.     lint.value = l_apic[LVT_LINT1];
  419.     printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]); 
  420.     error.value = l_apic[LVT_Err];
  421.     printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
  422. #endif
  423. }
  424.  
  425. /** Local APIC Timer Interrupt.
  426.  *
  427.  * @param n Interrupt vector number.
  428.  * @param stack Interrupted stack.
  429.  */
  430. void l_apic_timer_interrupt(int n, istate_t *istate)
  431. {
  432.     l_apic_eoi();
  433.     clock();
  434. }
  435.  
  436. /** Get Local APIC ID.
  437.  *
  438.  * @return Local APIC ID.
  439.  */
  440. __u8 l_apic_id(void)
  441. {
  442.     l_apic_id_t idreg;
  443.    
  444.     idreg.value = l_apic[L_APIC_ID];
  445.     return idreg.apic_id;
  446. }
  447.  
  448. /** Read from IO APIC register.
  449.  *
  450.  * @param address IO APIC register address.
  451.  *
  452.  * @return Content of the addressed IO APIC register.
  453.  */
  454. __u32 io_apic_read(__u8 address)
  455. {
  456.     io_regsel_t regsel;
  457.    
  458.     regsel.value = io_apic[IOREGSEL];
  459.     regsel.reg_addr = address;
  460.     io_apic[IOREGSEL] = regsel.value;
  461.     return io_apic[IOWIN];
  462. }
  463.  
  464. /** Write to IO APIC register.
  465.  *
  466.  * @param address IO APIC register address.
  467.  * @param Content to be written to the addressed IO APIC register.
  468.  */
  469. void io_apic_write(__u8 address, __u32 x)
  470. {
  471.     io_regsel_t regsel;
  472.    
  473.     regsel.value = io_apic[IOREGSEL];
  474.     regsel.reg_addr = address;
  475.     io_apic[IOREGSEL] = regsel.value;
  476.     io_apic[IOWIN] = x;
  477. }
  478.  
  479. /** Change some attributes of one item in I/O Redirection Table.
  480.  *
  481.  * @param pin IO APIC pin number.
  482.  * @param dest Interrupt destination address.
  483.  * @param v Interrupt vector to trigger.
  484.  * @param flags Flags.
  485.  */
  486. void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags)
  487. {
  488.     io_redirection_reg_t reg;
  489.     int dlvr = DELMOD_FIXED;
  490.    
  491.     if (flags & LOPRI)
  492.         dlvr = DELMOD_LOWPRI;
  493.  
  494.     reg.lo = io_apic_read(IOREDTBL + pin*2);
  495.     reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);
  496.    
  497.     reg.dest = dest;
  498.     reg.destmod = DESTMOD_LOGIC;
  499.     reg.trigger_mode = TRIGMOD_EDGE;
  500.     reg.intpol = POLARITY_HIGH;
  501.     reg.delmod = dlvr;
  502.     reg.intvec = v;
  503.  
  504.     io_apic_write(IOREDTBL + pin*2, reg.lo);
  505.     io_apic_write(IOREDTBL + pin*2 + 1, reg.hi);
  506. }
  507.  
  508. /** Mask IRQs in IO APIC.
  509.  *
  510.  * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
  511.  */
  512. void io_apic_disable_irqs(__u16 irqmask)
  513. {
  514.     io_redirection_reg_t reg;
  515.     int i, pin;
  516.    
  517.     for (i=0;i<16;i++) {
  518.         if (irqmask & (1<<i)) {
  519.             /*
  520.              * Mask the signal input in IO APIC if there is a
  521.              * mapping for the respective IRQ number.
  522.              */
  523.             pin = smp_irq_to_pin(i);
  524.             if (pin != -1) {
  525.                 reg.lo = io_apic_read(IOREDTBL + pin*2);
  526.                 reg.masked = true;
  527.                 io_apic_write(IOREDTBL + pin*2, reg.lo);
  528.             }
  529.            
  530.         }
  531.     }
  532. }
  533.  
  534. /** Unmask IRQs in IO APIC.
  535.  *
  536.  * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
  537.  */
  538. void io_apic_enable_irqs(__u16 irqmask)
  539. {
  540.     int i, pin;
  541.     io_redirection_reg_t reg;  
  542.    
  543.     for (i=0;i<16;i++) {
  544.         if (irqmask & (1<<i)) {
  545.             /*
  546.              * Unmask the signal input in IO APIC if there is a
  547.              * mapping for the respective IRQ number.
  548.              */
  549.             pin = smp_irq_to_pin(i);
  550.             if (pin != -1) {
  551.                 reg.lo = io_apic_read(IOREDTBL + pin*2);
  552.                 reg.masked = false;
  553.                 io_apic_write(IOREDTBL + pin*2, reg.lo);
  554.             }
  555.            
  556.         }
  557.     }
  558. }
  559.  
  560. #endif /* CONFIG_SMP */
  561.