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  1. /*
  2.  * Copyright (C) 2001-2004 Jakub Jermar
  3.  * Copyright (C) 2005 Sergey Bondari
  4.  * All rights reserved.
  5.  *
  6.  * Redistribution and use in source and binary forms, with or without
  7.  * modification, are permitted provided that the following conditions
  8.  * are met:
  9.  *
  10.  * - Redistributions of source code must retain the above copyright
  11.  *   notice, this list of conditions and the following disclaimer.
  12.  * - Redistributions in binary form must reproduce the above copyright
  13.  *   notice, this list of conditions and the following disclaimer in the
  14.  *   documentation and/or other materials provided with the distribution.
  15.  * - The name of the author may not be used to endorse or promote products
  16.  *   derived from this software without specific prior written permission.
  17.  *
  18.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  19.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  20.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28.  */
  29.  
  30. #ifndef __ia32_ASM_H__
  31. #define __ia32_ASM_H__
  32.  
  33. #include <arch/types.h>
  34. #include <config.h>
  35.  
  36. extern __u32 interrupt_handler_size;
  37.  
  38. extern void paging_on(void);
  39.  
  40. extern void interrupt_handlers(void);
  41.  
  42. extern void enable_l_apic_in_msr(void);
  43.  
  44.  
  45. extern void asm_delay_loop(__u32 t);
  46. extern void asm_fake_loop(__u32 t);
  47.  
  48.  
  49. /** Halt CPU
  50.  *
  51.  * Halt the current CPU until interrupt event.
  52.  */
  53. static inline void cpu_halt(void) { __asm__("hlt\n"); };
  54. static inline void cpu_sleep(void) { __asm__("hlt\n"); };
  55.  
  56. #define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \
  57.     { \
  58.     __native res; \
  59.     __asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
  60.     return res; \
  61.     }
  62.  
  63. #define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \
  64.     { \
  65.     __asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \
  66.     }
  67.  
  68. GEN_READ_REG(cr0);
  69. GEN_READ_REG(cr2);
  70. GEN_READ_REG(cr3);
  71. GEN_WRITE_REG(cr3);
  72.  
  73. GEN_READ_REG(dr0);
  74. GEN_READ_REG(dr1);
  75. GEN_READ_REG(dr2);
  76. GEN_READ_REG(dr3);
  77. GEN_READ_REG(dr6);
  78. GEN_READ_REG(dr7);
  79.  
  80. GEN_WRITE_REG(dr0);
  81. GEN_WRITE_REG(dr1);
  82. GEN_WRITE_REG(dr2);
  83. GEN_WRITE_REG(dr3);
  84. GEN_WRITE_REG(dr6);
  85. GEN_WRITE_REG(dr7);
  86.  
  87. /** Byte to port
  88.  *
  89.  * Output byte to port
  90.  *
  91.  * @param port Port to write to
  92.  * @param val Value to write
  93.  */
  94. static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
  95.  
  96. /** Word to port
  97.  *
  98.  * Output word to port
  99.  *
  100.  * @param port Port to write to
  101.  * @param val Value to write
  102.  */
  103. static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
  104.  
  105. /** Double word to port
  106.  *
  107.  * Output double word to port
  108.  *
  109.  * @param port Port to write to
  110.  * @param val Value to write
  111.  */
  112. static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
  113.  
  114. /** Byte from port
  115.  *
  116.  * Get byte from port
  117.  *
  118.  * @param port Port to read from
  119.  * @return Value read
  120.  */
  121. static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
  122.  
  123. /** Word from port
  124.  *
  125.  * Get word from port
  126.  *
  127.  * @param port Port to read from
  128.  * @return Value read
  129.  */
  130. static inline __u16 inw(__u16 port) { __u16 val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
  131.  
  132. /** Double word from port
  133.  *
  134.  * Get double word from port
  135.  *
  136.  * @param port Port to read from
  137.  * @return Value read
  138.  */
  139. static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
  140.  
  141. /** Enable interrupts.
  142.  *
  143.  * Enable interrupts and return previous
  144.  * value of EFLAGS.
  145.  *
  146.  * @return Old interrupt priority level.
  147.  */
  148. static inline ipl_t interrupts_enable(void)
  149. {
  150.     ipl_t v;
  151.     __asm__ volatile (
  152.         "pushf\n\t"
  153.         "popl %0\n\t"
  154.         "sti\n"
  155.         : "=r" (v)
  156.     );
  157.     return v;
  158. }
  159.  
  160. /** Disable interrupts.
  161.  *
  162.  * Disable interrupts and return previous
  163.  * value of EFLAGS.
  164.  *
  165.  * @return Old interrupt priority level.
  166.  */
  167. static inline ipl_t interrupts_disable(void)
  168. {
  169.     ipl_t v;
  170.     __asm__ volatile (
  171.         "pushf\n\t"
  172.         "popl %0\n\t"
  173.         "cli\n"
  174.         : "=r" (v)
  175.     );
  176.     return v;
  177. }
  178.  
  179. /** Restore interrupt priority level.
  180.  *
  181.  * Restore EFLAGS.
  182.  *
  183.  * @param ipl Saved interrupt priority level.
  184.  */
  185. static inline void interrupts_restore(ipl_t ipl)
  186. {
  187.     __asm__ volatile (
  188.         "pushl %0\n\t"
  189.         "popf\n"
  190.         : : "r" (ipl)
  191.     );
  192. }
  193.  
  194. /** Return interrupt priority level.
  195.  *
  196.  * @return EFLAFS.
  197.  */
  198. static inline ipl_t interrupts_read(void)
  199. {
  200.     ipl_t v;
  201.     __asm__ volatile (
  202.         "pushf\n\t"
  203.         "popl %0\n"
  204.         : "=r" (v)
  205.     );
  206.     return v;
  207. }
  208.  
  209. /** Return base address of current stack
  210.  *
  211.  * Return the base address of the current stack.
  212.  * The stack is assumed to be STACK_SIZE bytes long.
  213.  * The stack must start on page boundary.
  214.  */
  215. static inline __address get_stack_base(void)
  216. {
  217.     __address v;
  218.    
  219.     __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
  220.    
  221.     return v;
  222. }
  223.  
  224. static inline __u64 rdtsc(void)
  225. {
  226.     __u64 v;
  227.    
  228.     __asm__ volatile("rdtsc\n" : "=A" (v));
  229.    
  230.     return v;
  231. }
  232.  
  233. /** Return current IP address */
  234. static inline __address * get_ip()
  235. {
  236.     __address *ip;
  237.  
  238.     __asm__ volatile (
  239.         "mov %%eip, %0"
  240.         : "=r" (ip)
  241.         );
  242.     return ip;
  243. }
  244.  
  245. /** Invalidate TLB Entry.
  246.  *
  247.  * @param addr Address on a page whose TLB entry is to be invalidated.
  248.  */
  249. static inline void invlpg(__address addr)
  250. {
  251.     __asm__ volatile ("invlpg %0\n" :: "m" (*(__native *)addr));
  252. }
  253.  
  254. #endif
  255.