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  1. /*
  2.  * Copyright (C) 2001-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29.  /** @addtogroup amd64cpu amd64
  30.  * @ingroup cpu
  31.  * @{
  32.  */
  33. /** @file
  34.  */
  35.  
  36. #include <arch/cpu.h>
  37. #include <arch/cpuid.h>
  38. #include <arch/pm.h>
  39.  
  40. #include <arch.h>
  41. #include <arch/types.h>
  42. #include <print.h>
  43. #include <typedefs.h>
  44. #include <fpu_context.h>
  45.  
  46. /*
  47.  * Identification of CPUs.
  48.  * Contains only non-MP-Specification specific SMP code.
  49.  */
  50. #define AMD_CPUID_EBX   0x68747541
  51. #define AMD_CPUID_ECX   0x444d4163
  52. #define AMD_CPUID_EDX   0x69746e65
  53.  
  54. #define INTEL_CPUID_EBX 0x756e6547
  55. #define INTEL_CPUID_ECX 0x6c65746e
  56. #define INTEL_CPUID_EDX 0x49656e69
  57.  
  58.  
  59. enum vendor {
  60.     VendorUnknown=0,
  61.     VendorAMD,
  62.     VendorIntel
  63. };
  64.  
  65. static char *vendor_str[] = {
  66.     "Unknown Vendor",
  67.     "AuthenticAMD",
  68.     "GenuineIntel"
  69. };
  70.  
  71.  
  72. /** Setup flags on processor so that we can use the FPU
  73.  *
  74.  * cr0.osfxsr = 1 -> we do support fxstor/fxrestor
  75.  * cr0.em = 0 -> we do not emulate coprocessor
  76.  * cr0.mp = 1 -> we do want lazy context switch
  77.  */
  78. void cpu_setup_fpu(void)
  79. {
  80.     __asm__ volatile (
  81.         "movq %%cr0, %%rax;"
  82.         "btsq $1, %%rax;" /* cr0.mp */
  83.         "btrq $2, %%rax;"  /* cr0.em */
  84.         "movq %%rax, %%cr0;"
  85.  
  86.         "movq %%cr4, %%rax;"
  87.         "bts $9, %%rax;" /* cr4.osfxsr */
  88.         "movq %%rax, %%cr4;"
  89.         :
  90.         :
  91.         :"%rax"
  92.         );
  93. }
  94.  
  95. /** Set the TS flag to 1.
  96.  *
  97.  * If a thread accesses coprocessor, exception is run, which
  98.  * does a lazy fpu context switch.
  99.  *
  100.  */
  101. void fpu_disable(void)
  102. {
  103.     __asm__ volatile (
  104.         "mov %%cr0,%%rax;"
  105.         "bts $3,%%rax;"
  106.         "mov %%rax,%%cr0;"
  107.         :
  108.         :
  109.         :"%rax"
  110.         );
  111. }
  112.  
  113. void fpu_enable(void)
  114. {
  115.     __asm__ volatile (
  116.         "mov %%cr0,%%rax;"
  117.         "btr $3,%%rax;"
  118.         "mov %%rax,%%cr0;"
  119.         :
  120.         :
  121.         :"%rax"
  122.         ); 
  123. }
  124.  
  125. void cpu_arch_init(void)
  126. {
  127.     CPU->arch.tss = tss_p;
  128.     CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((__u8 *) CPU->arch.tss);
  129.     CPU->fpu_owner = NULL;
  130. }
  131.  
  132. void cpu_identify(void)
  133. {
  134.     cpu_info_t info;
  135.  
  136.     CPU->arch.vendor = VendorUnknown;
  137.     if (has_cpuid()) {
  138.         cpuid(0, &info);
  139.  
  140.         /*
  141.          * Check for AMD processor.
  142.          */
  143.         if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) {
  144.             CPU->arch.vendor = VendorAMD;
  145.         }
  146.  
  147.         /*
  148.          * Check for Intel processor.
  149.          */    
  150.         if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) {
  151.             CPU->arch.vendor = VendorIntel;
  152.         }
  153.                
  154.         cpuid(1, &info);
  155.         CPU->arch.family = (info.cpuid_eax>>8)&0xf;
  156.         CPU->arch.model = (info.cpuid_eax>>4)&0xf;
  157.         CPU->arch.stepping = (info.cpuid_eax>>0)&0xf;                      
  158.     }
  159. }
  160.  
  161. void cpu_print_report(cpu_t* m)
  162. {
  163.     printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",
  164.         m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping,
  165.         m->frequency_mhz);
  166. }
  167.  
  168.  /** @}
  169.  */
  170.  
  171.