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  1. /*
  2.  * Copyright (C) 2005 Ondrej Palkovsky
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #include <arch.h>
  30.  
  31. #include <arch/types.h>
  32.  
  33. #include <config.h>
  34.  
  35. #include <proc/thread.h>
  36. #include <arch/drivers/ega.h>
  37. #include <arch/vesa.h>
  38. #include <genarch/i8042/i8042.h>
  39. #include <arch/i8254.h>
  40. #include <arch/i8259.h>
  41.  
  42. #include <arch/bios/bios.h>
  43. #include <arch/mm/memory_init.h>
  44. #include <arch/cpu.h>
  45. #include <print.h>
  46. #include <arch/cpuid.h>
  47. #include <genarch/acpi/acpi.h>
  48. #include <panic.h>
  49. #include <interrupt.h>
  50. #include <arch/syscall.h>
  51. #include <arch/debugger.h>
  52. #include <syscall/syscall.h>
  53. #include <console/console.h>
  54.  
  55.  
  56. /** Disable I/O on non-privileged levels
  57.  *
  58.  * Clean IOPL(12,13) and NT(14) flags in EFLAGS register
  59.  */
  60. static void clean_IOPL_NT_flags(void)
  61. {
  62.     asm
  63.     (
  64.         "pushfq;"
  65.         "pop %%rax;"
  66.         "and $~(0x7000),%%rax;"
  67.         "pushq %%rax;"
  68.         "popfq;"
  69.         :
  70.         :
  71.         :"%rax"
  72.     );
  73. }
  74.  
  75. /** Disable alignment check
  76.  *
  77.  * Clean AM(18) flag in CR0 register
  78.  */
  79. static void clean_AM_flag(void)
  80. {
  81.     asm
  82.     (
  83.         "mov %%cr0,%%rax;"
  84.         "and $~(0x40000),%%rax;"
  85.         "mov %%rax,%%cr0;"
  86.         :
  87.         :
  88.         :"%rax"
  89.     );
  90. }
  91.  
  92. void arch_pre_mm_init(void)
  93. {
  94.     struct cpu_info cpuid_s;
  95.  
  96.     cpuid(AMD_CPUID_EXTENDED,&cpuid_s);
  97.     if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE)))
  98.         panic("Processor does not support No-execute pages.\n");
  99.  
  100.     cpuid(INTEL_CPUID_STANDARD,&cpuid_s);
  101.     if (! (cpuid_s.cpuid_edx & (1<<INTEL_FXSAVE)))
  102.         panic("Processor does not support FXSAVE/FXRESTORE.\n");
  103.    
  104.     if (! (cpuid_s.cpuid_edx & (1<<INTEL_SSE2)))
  105.         panic("Processor does not support SSE2 instructions.\n");
  106.  
  107.     /* Enable No-execute pages */
  108.     set_efer_flag(AMD_NXE_FLAG);
  109.     /* Enable FPU */
  110.     cpu_setup_fpu();
  111.  
  112.     /* Initialize segmentation */
  113.     pm_init();
  114.  
  115.         /* Disable I/O on nonprivileged levels
  116.      * clear the NT(nested-thread) flag
  117.      */
  118.     clean_IOPL_NT_flags();
  119.     /* Disable alignment check */
  120.     clean_AM_flag();
  121.  
  122.     if (config.cpu_active == 1) {
  123.         bios_init();
  124.         i8259_init();   /* PIC */
  125.         i8254_init();   /* hard clock */
  126.  
  127.         #ifdef CONFIG_SMP
  128.         exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown",
  129.                  tlb_shootdown_ipi);
  130.         #endif /* CONFIG_SMP */
  131.     }
  132. }
  133.  
  134. void arch_post_mm_init(void)
  135. {
  136.     if (config.cpu_active == 1) {
  137. #ifdef CONFIG_FB
  138.         if (vesa_present())
  139.             vesa_init();
  140.         else
  141. #endif
  142.             ega_init(); /* video */
  143.         /* Enable debugger */
  144.         debugger_init();
  145.         /* Merge all memory zones to 1 big zone */
  146.         zone_merge_all();
  147.     }
  148.     /* Setup fast SYSCALL/SYSRET */
  149.     syscall_setup_cpu();
  150.    
  151. }
  152.  
  153. void arch_pre_smp_init(void)
  154. {
  155.     if (config.cpu_active == 1) {
  156.         memory_print_map();
  157.        
  158.         #ifdef CONFIG_SMP
  159.         acpi_init();
  160.         #endif /* CONFIG_SMP */
  161.     }
  162. }
  163.  
  164. void arch_post_smp_init(void)
  165. {
  166.     i8042_init();   /* keyboard controller */
  167. }
  168.  
  169. void calibrate_delay_loop(void)
  170. {
  171.     i8254_calibrate_delay_loop();
  172.     i8254_normal_operation();
  173. }
  174.  
  175. /** Set thread-local-storage pointer
  176.  *
  177.  * TLS pointer is set in FS register. Unfortunately the 64-bit
  178.  * part can be set only in CPL0 mode.
  179.  *
  180.  * The specs say, that on %fs:0 there is stored contents of %fs register,
  181.  * we need not to go to CPL0 to read it.
  182.  */
  183. __native sys_tls_set(__native addr)
  184. {
  185.     THREAD->arch.tls = addr;
  186.     write_msr(AMD_MSR_FS, addr);
  187.     return 0;
  188. }
  189.  
  190. /** Acquire console back for kernel
  191.  *
  192.  */
  193. void arch_grab_console(void)
  194. {
  195.     i8042_grab();
  196. }
  197. /** Return console to userspace
  198.  *
  199.  */
  200. void arch_release_console(void)
  201. {
  202.     i8042_release();
  203. }
  204.