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  1. /*
  2.  * Copyright (C) 2005 Ondrej Palkovsky
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #include <arch.h>
  30.  
  31. #include <arch/types.h>
  32.  
  33. #include <config.h>
  34.  
  35. #include <proc/thread.h>
  36. #include <arch/ega.h>
  37. #include <genarch/i8042/i8042.h>
  38. #include <arch/i8254.h>
  39. #include <arch/i8259.h>
  40.  
  41. #include <arch/bios/bios.h>
  42. #include <arch/mm/memory_init.h>
  43. #include <arch/cpu.h>
  44. #include <print.h>
  45. #include <arch/cpuid.h>
  46. #include <genarch/acpi/acpi.h>
  47. #include <panic.h>
  48. #include <interrupt.h>
  49. #include <arch/syscall.h>
  50. #include <arch/debugger.h>
  51. #include <syscall/syscall.h>
  52.  
  53.  
  54. /** Disable I/O on non-privileged levels
  55.  *
  56.  * Clean IOPL(12,13) and NT(14) flags in EFLAGS register
  57.  */
  58. static void clean_IOPL_NT_flags(void)
  59. {
  60.     asm
  61.     (
  62.         "pushfq;"
  63.         "pop %%rax;"
  64.         "and $~(0x7000),%%rax;"
  65.         "pushq %%rax;"
  66.         "popfq;"
  67.         :
  68.         :
  69.         :"%rax"
  70.     );
  71. }
  72.  
  73. /** Disable alignment check
  74.  *
  75.  * Clean AM(18) flag in CR0 register
  76.  */
  77. static void clean_AM_flag(void)
  78. {
  79.     asm
  80.     (
  81.         "mov %%cr0,%%rax;"
  82.         "and $~(0x40000),%%rax;"
  83.         "mov %%rax,%%cr0;"
  84.         :
  85.         :
  86.         :"%rax"
  87.     );
  88. }
  89.  
  90. void arch_pre_mm_init(void)
  91. {
  92.     struct cpu_info cpuid_s;
  93.  
  94.     cpuid(AMD_CPUID_EXTENDED,&cpuid_s);
  95.     if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE)))
  96.         panic("Processor does not support No-execute pages.\n");
  97.  
  98.     cpuid(INTEL_CPUID_STANDARD,&cpuid_s);
  99.     if (! (cpuid_s.cpuid_edx & (1<<INTEL_FXSAVE)))
  100.         panic("Processor does not support FXSAVE/FXRESTORE.\n");
  101.    
  102.     if (! (cpuid_s.cpuid_edx & (1<<INTEL_SSE2)))
  103.         panic("Processor does not support SSE2 instructions.\n");
  104.  
  105.     /* Enable No-execute pages */
  106.     set_efer_flag(AMD_NXE_FLAG);
  107.     /* Enable FPU */
  108.     cpu_setup_fpu();
  109.  
  110.     /* Initialize segmentation */
  111.     pm_init();
  112.  
  113.         /* Disable I/O on nonprivileged levels
  114.      * clear the NT(nested-thread) flag
  115.      */
  116.     clean_IOPL_NT_flags();
  117.     /* Disable alignment check */
  118.     clean_AM_flag();
  119.  
  120.     if (config.cpu_active == 1) {
  121.         bios_init();
  122.         i8259_init();   /* PIC */
  123.         i8254_init();   /* hard clock */
  124.  
  125.         #ifdef CONFIG_SMP
  126.         exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown",
  127.                  tlb_shootdown_ipi);
  128.         #endif /* CONFIG_SMP */
  129.     }
  130. }
  131.  
  132. void arch_post_mm_init(void)
  133. {
  134.     if (config.cpu_active == 1) {
  135.         ega_init(); /* video */
  136.         /* Enable debugger */
  137.         debugger_init();
  138.     }
  139.     /* Setup fast SYSCALL/SYSRET */
  140.     syscall_setup_cpu();
  141.    
  142. }
  143.  
  144. void arch_pre_smp_init(void)
  145. {
  146.     if (config.cpu_active == 1) {
  147.         memory_print_map();
  148.        
  149.         #ifdef CONFIG_SMP
  150.         acpi_init();
  151.         #endif /* CONFIG_SMP */
  152.     }
  153. }
  154.  
  155. void arch_post_smp_init(void)
  156. {
  157.     i8042_init();   /* keyboard controller */
  158. }
  159.  
  160. void calibrate_delay_loop(void)
  161. {
  162.     i8254_calibrate_delay_loop();
  163.     i8254_normal_operation();
  164. }
  165.  
  166. /** Set thread-local-storage pointer
  167.  *
  168.  * TLS pointer is set in FS register. Unfortunately the 64-bit
  169.  * part can be set only in CPL0 mode.
  170.  *
  171.  * The specs say, that on %fs:0 there is stored contents of %fs register,
  172.  * we need not to go to CPL0 to read it.
  173.  */
  174. __native sys_tls_set(__native addr)
  175. {
  176.     THREAD->tls = addr;
  177.     write_msr(AMD_MSR_FS, addr);
  178.     return 0;
  179. }
  180.