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<title>Architecture overview</title>
<section>
<title>Scheme</title>
<para>
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</section>
<section>
<title>Monolithic microkernel</title>
<para>
Though HelenOS was initially planned as a microkernel, we where trying to avoid several issues, connected
with microkernels, such as much higher overhead during memory management and hardware operations. For this reason
some of the subsytems, that are to be implmented as servers in classic microkernel design, where implemented
as a part of kernel, thus minimizing this overhead.
</para>
<formalpara>
<title>Memory management</title>
<para>
Unlike the classic microkernel, HelenOS has all its memory management functionality in the kernel, available to the memory
management server via the set of syscalls.
</para>
</formalpara>
<formalpara>
<title>Kernel device drivers</title>
<para>
HelenOS kernel has some of the very basic device drivers
<itemizedlist>
<listitem>ACPI</listitem>
<listitem>APIC</listitem>
<listitem>SMP configuration</listitem>
<listitem>System clock</listitem>
<listitem>Interrupt controllers</listitem>
<listitem>Console</listitem>
<listitem>VESA & frame buffer</listitem>
</itemizedlist>
</para>
</formalpara>
</section>
<section>
<title>Kernel primitives</title>
<para>
<termdef><glossterm>Thread</glossterm> is the basic execution primitive.</termdef>
</para>
<para>
<termdef><glossterm>Thread context</glossterm> represents state of the <emphasis>thread</emphasis>. Contains registers state, FPU state, stack(s).</termdef>
</para>
<para>
<termdef><glossterm>Task</glossterm> </termdef>
</para>
<para>
<termdef>
<glossterm>Address space area</glossterm> is a mutually disjunctive range of memory with the code, stack and data.
</termdef>
</para>
<para>
<termdef>
<glossterm>Address space</glossterm> is a aggregating entity for address space areas, connecting them to the task.
</termdef>
</para> 1
</section>
<section>
<title>IPC</title>
<para>
Due to the high intertask communication traffic, IPC becomes critical subsystem for microkernels, putting high demands on the
speed, latency and reliability of IPC model and implementation. HelenOS IPC is designed in analogy with telephone communication.
Each task has an <emphasis>answerbox</emphasis> and a set of <emphasis>phones</emphasis> to call another tasks' answerboxes. Communication
is possible after the link establishment, and can be either <emphasis>asynchronious</emphasis> or <emphasis>synchronious</emphasis>.
</para>
</section>
<section>
<para>Task ID - unique 64 bit number. Used for syscalls.</para>
<para>Contains threads</para>
<para>Address space is created per task</para>
<para>Memory mapping is per task</para>
<para>Context per thread. (Note 2 stacks on IA64).</para>
<para>IPC answer box associated per task</para>
<title>Memory management</title>
<para>
Zones - linked list (not many zones, so we can afford it. Can be replaced with B-tree in the future)
Number of zones depends on HW tables. Describe zone allocation/deallocation algoritm
</para>
<para>Page tables. 4 level hierarchical and hash directly supported. B+ Tree can be implemented.</para>
<para>For paging there is an abstract layer</para>
<para>TLB shootdown implementation (update TLB upon mapping update/remove).
TLB shootdown ASID/ASID:PAGE/ALL.
TLB shootdown requests can come in asynchroniously
so there is a cache of TLB shootdown requests. Upon cache overflow TLB shootdown ALL is executed</para>
<para>
Address spaces. Address space area (B+ tree). Only for uspace. Set of syscalls (shrink/extend etc).
Special address space area type - device - prohibits shrink/extend syscalls to call on it.
Address space has link to mapping tables (hierarchical - per Address space, hash - global tables).
</para>
</section>
</chapter>