Subversion Repositories HelenOS

Rev

Rev 863 | Rev 877 | Go to most recent revision | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed

  1. /*
  2.  * Copyright (C) 2005 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. #include <arch/mm/tlb.h>
  30. #include <mm/tlb.h>
  31. #include <arch/mm/frame.h>
  32. #include <arch/mm/page.h>
  33. #include <arch/mm/mmu.h>
  34. #include <print.h>
  35. #include <arch/types.h>
  36. #include <typedefs.h>
  37. #include <config.h>
  38. #include <arch/trap/trap.h>
  39. #include <panic.h>
  40. #include <arch/asm.h>
  41. #include <symtab.h>
  42.  
  43. char *context_encoding[] = {
  44.     "Primary",
  45.     "Secondary",
  46.     "Nucleus",
  47.     "Reserved"
  48. };
  49.  
  50. /** Initialize ITLB and DTLB.
  51.  *
  52.  * The goal of this function is to disable MMU
  53.  * so that both TLBs can be purged and new
  54.  * kernel 4M locked entry can be installed.
  55.  * After TLB is initialized, MMU is enabled
  56.  * again.
  57.  *
  58.  * Switching MMU off imposes the requirement for
  59.  * the kernel to run in identity mapped environment.
  60.  */
  61. void tlb_arch_init(void)
  62. {
  63.     tlb_tag_access_reg_t tag;
  64.     tlb_data_t data;
  65.     frame_address_t fr;
  66.     page_address_t pg;
  67.  
  68.     fr.address = config.base;
  69.     pg.address = config.base;
  70.  
  71.     immu_disable();
  72.     dmmu_disable();
  73.    
  74.     /*
  75.      * We do identity mapping of 4M-page at 4M.
  76.      */
  77.     tag.value = 0;
  78.     tag.vpn = pg.vpn;
  79.  
  80.     itlb_tag_access_write(tag.value);
  81.     dtlb_tag_access_write(tag.value);
  82.  
  83.     data.value = 0;
  84.     data.v = true;
  85.     data.size = PAGESIZE_4M;
  86.     data.pfn = fr.pfn;
  87.     data.l = true;
  88.     data.cp = 1;
  89.     data.cv = 1;
  90.     data.p = true;
  91.     data.w = true;
  92.     data.g = true;
  93.  
  94.     itlb_data_in_write(data.value);
  95.     dtlb_data_in_write(data.value);
  96.  
  97.     /*
  98.      * Register window traps can occur before MMU is enabled again.
  99.      * This ensures that any such traps will be handled from
  100.      * kernel identity mapped trap handler.
  101.      */
  102.     trap_switch_trap_table();
  103.    
  104.     tlb_invalidate_all();
  105.  
  106.     dmmu_enable();
  107.     immu_enable();
  108.    
  109.     /*
  110.      * Quick hack: map frame buffer
  111.      */
  112.     fr.address = 0x1C901000000ULL;
  113.     pg.address = 0xc0000000;
  114.  
  115.     tag.value = 0;
  116.     tag.vpn = pg.vpn;
  117.  
  118.     dtlb_tag_access_write(tag.value);
  119.  
  120.     data.value = 0;
  121.     data.v = true;
  122.     data.size = PAGESIZE_4M;
  123.     data.pfn = fr.pfn;
  124.     data.l = true;
  125.     data.cp = 0;
  126.     data.cv = 0;
  127.     data.p = true;
  128.     data.w = true;
  129.     data.g = true;
  130.  
  131.     dtlb_data_in_write(data.value);
  132.  
  133. }
  134.  
  135. /** ITLB miss handler. */
  136. void fast_instruction_access_mmu_miss(void)
  137. {
  138.     panic("%s\n", __FUNCTION__);
  139. }
  140.  
  141. /** DTLB miss handler. */
  142. void fast_data_access_mmu_miss(void)
  143. {
  144.     tlb_sfsr_reg_t status;
  145.     __address address, tpc;
  146.     char *tpc_str;
  147.    
  148.     status.value = dtlb_sfsr_read();
  149.     address = dtlb_sfar_read();
  150.     tpc = tpc_read();
  151.     tpc_str = get_symtab_entry(tpc);
  152.  
  153.     printf("ASI=%B, Context=%s\n", status.asi, context_encoding[status.ct]);
  154.     printf("Faulting address: %P\n", dtlb_sfar_read());
  155.     printf("TPC=%P, (%s)\n", tpc, tpc_str ? tpc_str : "?");
  156.     panic("%s\n", __FUNCTION__);
  157. }
  158.  
  159. /** DTLB protection fault handler. */
  160. void fast_data_access_protection(void)
  161. {
  162.     panic("%s\n", __FUNCTION__);
  163. }
  164.  
  165. /** Print contents of both TLBs. */
  166. void tlb_print(void)
  167. {
  168.     int i;
  169.     tlb_data_t d;
  170.     tlb_tag_read_reg_t t;
  171.    
  172.     printf("I-TLB contents:\n");
  173.     for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
  174.         d.value = itlb_data_access_read(i);
  175.         t.value = itlb_tag_read_read(i);
  176.        
  177.         printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
  178.             i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
  179.     }
  180.  
  181.     printf("D-TLB contents:\n");
  182.     for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
  183.         d.value = dtlb_data_access_read(i);
  184.         t.value = dtlb_tag_read_read(i);
  185.        
  186.         printf("%d: vpn=%Q, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%X, diag=%X, pfn=%X, soft=%X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
  187.             i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
  188.     }
  189.  
  190. }
  191.  
  192. /** Invalidate all unlocked ITLB and DTLB entries. */
  193. void tlb_invalidate_all(void)
  194. {
  195.     int i;
  196.     tlb_data_t d;
  197.     tlb_tag_read_reg_t t;
  198.  
  199.     for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
  200.         d.value = itlb_data_access_read(i);
  201.         if (!d.l) {
  202.             t.value = itlb_tag_read_read(i);
  203.             d.v = false;
  204.             itlb_tag_access_write(t.value);
  205.             itlb_data_access_write(i, d.value);
  206.         }
  207.     }
  208.    
  209.     for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
  210.         d.value = dtlb_data_access_read(i);
  211.         if (!d.l) {
  212.             t.value = dtlb_tag_read_read(i);
  213.             d.v = false;
  214.             dtlb_tag_access_write(t.value);
  215.             dtlb_data_access_write(i, d.value);
  216.         }
  217.     }
  218.    
  219. }
  220.  
  221. /** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
  222.  *
  223.  * @param asid Address Space ID.
  224.  */
  225. void tlb_invalidate_asid(asid_t asid)
  226. {
  227.     /* TODO: write asid to some Context register and encode the register in second parameter below. */
  228.     itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
  229.     dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
  230. }
  231.  
  232. /** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
  233.  *
  234.  * @param asid Address Space ID.
  235.  * @param page First page which to sweep out from ITLB and DTLB.
  236.  * @param cnt Number of ITLB and DTLB entries to invalidate.
  237.  */
  238. void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
  239. {
  240.     int i;
  241.    
  242.     for (i = 0; i < cnt; i++) {
  243.         /* TODO: write asid to some Context register and encode the register in second parameter below. */
  244.         itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
  245.         dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
  246.     }
  247. }
  248.