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  1. /*
  2.  * Copyright (c) 2001-2004 Jakub Jermar
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup ia32   
  30.  * @{
  31.  */
  32. /** @file
  33.  */
  34.  
  35. #ifndef KERN_ia32_APIC_H_
  36. #define KERN_ia32_APIC_H_
  37.  
  38. #include <arch/types.h>
  39. #include <cpu.h>
  40.  
  41. #define FIXED       (0<<0)
  42. #define LOPRI       (1<<0)
  43.  
  44. #define APIC_ID_COUNT   16
  45.  
  46. /* local APIC macros */
  47. #define IPI_INIT    0
  48. #define IPI_STARTUP 0
  49.  
  50. /** Delivery modes. */
  51. #define DELMOD_FIXED    0x0
  52. #define DELMOD_LOWPRI   0x1
  53. #define DELMOD_SMI  0x2
  54. /* 0x3 reserved */
  55. #define DELMOD_NMI  0x4
  56. #define DELMOD_INIT 0x5
  57. #define DELMOD_STARTUP  0x6
  58. #define DELMOD_EXTINT   0x7
  59.  
  60. /** Destination modes. */
  61. #define DESTMOD_PHYS    0x0
  62. #define DESTMOD_LOGIC   0x1
  63.  
  64. /** Trigger Modes. */
  65. #define TRIGMOD_EDGE    0x0
  66. #define TRIGMOD_LEVEL   0x1
  67.  
  68. /** Levels. */
  69. #define LEVEL_DEASSERT  0x0
  70. #define LEVEL_ASSERT    0x1
  71.  
  72. /** Destination Shorthands. */
  73. #define SHORTHAND_NONE      0x0
  74. #define SHORTHAND_SELF      0x1
  75. #define SHORTHAND_ALL_INCL  0x2
  76. #define SHORTHAND_ALL_EXCL  0x3
  77.  
  78. /** Interrupt Input Pin Polarities. */
  79. #define POLARITY_HIGH   0x0
  80. #define POLARITY_LOW    0x1
  81.  
  82. /** Divide Values. (Bit 2 is always 0) */
  83. #define DIVIDE_2    0x0
  84. #define DIVIDE_4    0x1
  85. #define DIVIDE_8    0x2
  86. #define DIVIDE_16   0x3
  87. #define DIVIDE_32   0x8
  88. #define DIVIDE_64   0x9
  89. #define DIVIDE_128  0xa
  90. #define DIVIDE_1    0xb
  91.  
  92. /** Timer Modes. */
  93. #define TIMER_ONESHOT   0x0
  94. #define TIMER_PERIODIC  0x1
  95.  
  96. /** Delivery status. */
  97. #define DELIVS_IDLE 0x0
  98. #define DELIVS_PENDING  0x1
  99.  
  100. /** Destination masks. */
  101. #define DEST_ALL    0xff
  102.  
  103. /** Dest format models. */
  104. #define MODEL_FLAT  0xf
  105. #define MODEL_CLUSTER   0x0
  106.  
  107. /** Interrupt Command Register. */
  108. #define ICRlo       (0x300 / sizeof(uint32_t))
  109. #define ICRhi       (0x310 / sizeof(uint32_t))
  110. typedef struct {
  111.     union {
  112.         uint32_t lo;
  113.         struct {
  114.             uint8_t vector;         /**< Interrupt Vector. */
  115.             unsigned delmod : 3;        /**< Delivery Mode. */
  116.             unsigned destmod : 1;       /**< Destination Mode. */
  117.             unsigned delivs : 1;        /**< Delivery status (RO). */
  118.             unsigned : 1;           /**< Reserved. */
  119.             unsigned level : 1;     /**< Level. */
  120.             unsigned trigger_mode : 1;  /**< Trigger Mode. */
  121.             unsigned : 2;           /**< Reserved. */
  122.             unsigned shorthand : 2;     /**< Destination Shorthand. */
  123.             unsigned : 12;          /**< Reserved. */
  124.         } __attribute__ ((packed));
  125.     };
  126.     union {
  127.         uint32_t hi;
  128.         struct {
  129.             unsigned : 24;          /**< Reserved. */
  130.             uint8_t dest;           /**< Destination field. */
  131.         } __attribute__ ((packed));
  132.     };
  133. } __attribute__ ((packed)) icr_t;
  134.  
  135. /* End Of Interrupt. */
  136. #define EOI     (0x0b0 / sizeof(uint32_t))
  137.  
  138. /** Error Status Register. */
  139. #define ESR     (0x280 / sizeof(uint32_t))
  140. typedef union {
  141.     uint32_t value;
  142.     uint8_t err_bitmap;
  143.     struct {
  144.         unsigned send_checksum_error : 1;
  145.         unsigned receive_checksum_error : 1;
  146.         unsigned send_accept_error : 1;
  147.         unsigned receive_accept_error : 1;
  148.         unsigned : 1;
  149.         unsigned send_illegal_vector : 1;
  150.         unsigned received_illegal_vector : 1;
  151.         unsigned illegal_register_address : 1;
  152.         unsigned : 24;
  153.     } __attribute__ ((packed));
  154. } esr_t;
  155.  
  156. /* Task Priority Register */
  157. #define TPR     (0x080 / sizeof(uint32_t))
  158. typedef union {
  159.     uint32_t value;
  160.     struct {
  161.         unsigned pri_sc : 4;        /**< Task Priority Sub-Class. */
  162.         unsigned pri : 4;       /**< Task Priority. */
  163.     } __attribute__ ((packed));
  164. } tpr_t;
  165.  
  166. /** Spurious-Interrupt Vector Register. */
  167. #define SVR     (0x0f0 / sizeof(uint32_t))
  168. typedef union {
  169.     uint32_t value;
  170.     struct {
  171.         uint8_t vector;         /**< Spurious Vector. */
  172.         unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable. */
  173.         unsigned focus_checking : 1;    /**< Focus Processor Checking. */
  174.         unsigned : 22;          /**< Reserved. */
  175.     } __attribute__ ((packed));
  176. } svr_t;
  177.  
  178. /** Time Divide Configuration Register. */
  179. #define TDCR        (0x3e0 / sizeof(uint32_t))
  180. typedef union {
  181.     uint32_t value;
  182.     struct {
  183.         unsigned div_value : 4;     /**< Divide Value, bit 2 is always 0. */
  184.         unsigned : 28;          /**< Reserved. */
  185.     } __attribute__ ((packed));
  186. } tdcr_t;
  187.  
  188. /* Initial Count Register for Timer */
  189. #define ICRT        (0x380 / sizeof(uint32_t))
  190.  
  191. /* Current Count Register for Timer */
  192. #define CCRT        (0x390 / sizeof(uint32_t))
  193.  
  194. /** LVT Timer register. */
  195. #define LVT_Tm      (0x320 / sizeof(uint32_t))
  196. typedef union {
  197.     uint32_t value;
  198.     struct {
  199.         uint8_t vector;     /**< Local Timer Interrupt vector. */
  200.         unsigned : 4;       /**< Reserved. */
  201.         unsigned delivs : 1;    /**< Delivery status (RO). */
  202.         unsigned : 3;       /**< Reserved. */
  203.         unsigned masked : 1;    /**< Interrupt Mask. */
  204.         unsigned mode : 1;  /**< Timer Mode. */
  205.         unsigned : 14;      /**< Reserved. */
  206.     } __attribute__ ((packed));
  207. } lvt_tm_t;
  208.  
  209. /** LVT LINT registers. */
  210. #define LVT_LINT0   (0x350 / sizeof(uint32_t))
  211. #define LVT_LINT1   (0x360 / sizeof(uint32_t))
  212. typedef union {
  213.     uint32_t value;
  214.     struct {
  215.         uint8_t vector;         /**< LINT Interrupt vector. */
  216.         unsigned delmod : 3;        /**< Delivery Mode. */
  217.         unsigned : 1;           /**< Reserved. */
  218.         unsigned delivs : 1;        /**< Delivery status (RO). */
  219.         unsigned intpol : 1;        /**< Interrupt Input Pin Polarity. */
  220.         unsigned irr : 1;       /**< Remote IRR (RO). */
  221.         unsigned trigger_mode : 1;  /**< Trigger Mode. */
  222.         unsigned masked : 1;        /**< Interrupt Mask. */
  223.         unsigned : 15;          /**< Reserved. */
  224.     } __attribute__ ((packed));
  225. } lvt_lint_t;
  226.  
  227. /** LVT Error register. */
  228. #define LVT_Err     (0x370 / sizeof(uint32_t))
  229. typedef union {
  230.     uint32_t value;
  231.     struct {
  232.         uint8_t vector;     /**< Local Timer Interrupt vector. */
  233.         unsigned : 4;       /**< Reserved. */
  234.         unsigned delivs : 1;    /**< Delivery status (RO). */
  235.         unsigned : 3;       /**< Reserved. */
  236.         unsigned masked : 1;    /**< Interrupt Mask. */
  237.         unsigned : 15;      /**< Reserved. */
  238.     } __attribute__ ((packed));
  239. } lvt_error_t;
  240.  
  241. /** Local APIC ID Register. */
  242. #define L_APIC_ID   (0x020 / sizeof(uint32_t))
  243. typedef union {
  244.     uint32_t value;
  245.     struct {
  246.         unsigned : 24;      /**< Reserved. */
  247.         uint8_t apic_id;        /**< Local APIC ID. */
  248.     } __attribute__ ((packed));
  249. } l_apic_id_t;
  250.  
  251. /** Local APIC Version Register */
  252. #define LAVR        (0x030 / sizeof(uint32_t))
  253. #define LAVR_Mask   0xff
  254. #define is_local_apic(x)    (((x) & LAVR_Mask & 0xf0) == 0x1)
  255. #define is_82489DX_apic(x)  ((((x) & LAVR_Mask & 0xf0) == 0x0))
  256. #define is_local_xapic(x)   (((x) & LAVR_Mask) == 0x14)
  257.  
  258. /** Logical Destination Register. */
  259. #define  LDR        (0x0d0 / sizeof(uint32_t))
  260. typedef union {
  261.     uint32_t value;
  262.     struct {
  263.         unsigned : 24;      /**< Reserved. */
  264.         uint8_t id;     /**< Logical APIC ID. */
  265.     } __attribute__ ((packed));
  266. } ldr_t;
  267.  
  268. /** Destination Format Register. */
  269. #define DFR     (0x0e0 / sizeof(uint32_t))
  270. typedef union {
  271.     uint32_t value;
  272.     struct {
  273.         unsigned : 28;      /**< Reserved, all ones. */
  274.         unsigned model : 4; /**< Model. */
  275.     } __attribute__ ((packed));
  276. } dfr_t;
  277.  
  278. /* IO APIC */
  279. #define IOREGSEL    (0x00 / sizeof(uint32_t))
  280. #define IOWIN       (0x10 / sizeof(uint32_t))
  281.  
  282. #define IOAPICID    0x00
  283. #define IOAPICVER   0x01
  284. #define IOAPICARB   0x02
  285. #define IOREDTBL    0x10
  286.  
  287. /** I/O Register Select Register. */
  288. typedef union {
  289.     uint32_t value;
  290.     struct {
  291.         uint8_t reg_addr;       /**< APIC Register Address. */
  292.         unsigned : 24;      /**< Reserved. */
  293.     } __attribute__ ((packed));
  294. } io_regsel_t;
  295.  
  296. /** I/O Redirection Register. */
  297. typedef struct io_redirection_reg {
  298.     union {
  299.         uint32_t lo;
  300.         struct {
  301.             uint8_t intvec;         /**< Interrupt Vector. */
  302.             unsigned delmod : 3;        /**< Delivery Mode. */
  303.             unsigned destmod : 1;       /**< Destination mode. */
  304.             unsigned delivs : 1;        /**< Delivery status (RO). */
  305.             unsigned intpol : 1;        /**< Interrupt Input Pin Polarity. */
  306.             unsigned irr : 1;       /**< Remote IRR (RO). */
  307.             unsigned trigger_mode : 1;  /**< Trigger Mode. */
  308.             unsigned masked : 1;        /**< Interrupt Mask. */
  309.             unsigned : 15;          /**< Reserved. */
  310.         } __attribute__ ((packed));
  311.     };
  312.     union {
  313.         uint32_t hi;
  314.         struct {
  315.             unsigned : 24;          /**< Reserved. */
  316.             uint8_t dest : 8;           /**< Destination Field. */
  317.         } __attribute__ ((packed));
  318.     };
  319.    
  320. } __attribute__ ((packed)) io_redirection_reg_t;
  321.  
  322.  
  323. /** IO APIC Identification Register. */
  324. typedef union {
  325.     uint32_t value;
  326.     struct {
  327.         unsigned : 24;      /**< Reserved. */
  328.         unsigned apic_id : 4;   /**< IO APIC ID. */
  329.         unsigned : 4;       /**< Reserved. */
  330.     } __attribute__ ((packed));
  331. } io_apic_id_t;
  332.  
  333. extern volatile uint32_t *l_apic;
  334. extern volatile uint32_t *io_apic;
  335.  
  336. extern uint32_t apic_id_mask;
  337.  
  338. extern void apic_init(void);
  339.  
  340. extern void l_apic_init(void);
  341. extern void l_apic_eoi(void);
  342. extern int l_apic_broadcast_custom_ipi(uint8_t vector);
  343. extern int l_apic_send_init_ipi(uint8_t apicid);
  344. extern void l_apic_debug(void);
  345. extern uint8_t l_apic_id(void);
  346.  
  347. extern uint32_t io_apic_read(uint8_t address);
  348. extern void io_apic_write(uint8_t address , uint32_t x);
  349. extern void io_apic_change_ioredtbl(uint8_t pin, uint8_t dest, uint8_t v, int flags);
  350. extern void io_apic_disable_irqs(uint16_t irqmask);
  351. extern void io_apic_enable_irqs(uint16_t irqmask);
  352.  
  353. #endif
  354.  
  355. /** @}
  356.  */
  357.