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  1. /*
  2.  * Copyright (c) 2007 Petr Stepan
  3.  * All rights reserved.
  4.  *
  5.  * Redistribution and use in source and binary forms, with or without
  6.  * modification, are permitted provided that the following conditions
  7.  * are met:
  8.  *
  9.  * - Redistributions of source code must retain the above copyright
  10.  *   notice, this list of conditions and the following disclaimer.
  11.  * - Redistributions in binary form must reproduce the above copyright
  12.  *   notice, this list of conditions and the following disclaimer in the
  13.  *   documentation and/or other materials provided with the distribution.
  14.  * - The name of the author may not be used to endorse or promote products
  15.  *   derived from this software without specific prior written permission.
  16.  *
  17.  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18.  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19.  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20.  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21.  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22.  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23.  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24.  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25.  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26.  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27.  */
  28.  
  29. /** @addtogroup arm32
  30.  * @{
  31.  */
  32. /** @file
  33.  *  @brief Exception handlers and exception initialization routines.
  34.  */
  35.  
  36. #include <arch/exception.h>
  37. #include <arch/debug/print.h>
  38. #include <arch/memstr.h>
  39. #include <arch/regutils.h>
  40. #include <interrupt.h>
  41. #include <arch/machine.h>
  42. #include <arch/mm/page_fault.h>
  43. #include <print.h>
  44. #include <syscall/syscall.h>
  45. #include <udebug/udebug.h>
  46.  
  47. /** Offset used in calculation of exception handler's relative address.
  48.  *
  49.  * @see install_handler()
  50.  */
  51. #define PREFETCH_OFFSET      0x8
  52.  
  53. /** LDR instruction's code */
  54. #define LDR_OPCODE           0xe59ff000
  55.  
  56. /** Number of exception vectors. */
  57. #define EXC_VECTORS          8
  58.  
  59. /** Size of memory block occupied by exception vectors. */
  60. #define EXC_VECTORS_SIZE     (EXC_VECTORS * 4)
  61.  
  62. /** Switches to kernel stack and saves all registers there.
  63.  *
  64.  * Temporary exception stack is used to save a few registers
  65.  * before stack switch takes place.
  66.  */
  67. inline static void setup_stack_and_save_regs()
  68. {
  69.     asm volatile(
  70.         "ldr r13, =exc_stack        \n"
  71.         "stmfd r13!, {r0}       \n"
  72.         "mrs r0, spsr           \n"
  73.         "and r0, r0, #0x1f      \n"
  74.         "cmp r0, #0x10          \n"
  75.         "bne 1f             \n"
  76.  
  77.         /* prev mode was usermode */
  78.         "ldmfd r13!, {r0}       \n"
  79.         "ldr r13, =supervisor_sp    \n"
  80.         "ldr r13, [r13]         \n"
  81.         "stmfd r13!, {lr}       \n"
  82.         "stmfd r13!, {r0-r12}       \n"
  83.         "stmfd r13!, {r13, lr}^     \n"
  84.         "mrs r0, spsr           \n"
  85.         "stmfd r13!, {r0}       \n"
  86.         "b 2f               \n"
  87.  
  88.         /* mode was not usermode */
  89.     "1:\n"
  90.         "stmfd r13!, {r1, r2, r3}   \n"
  91.         "mrs r1, cpsr           \n"
  92.         "mov r2, lr         \n"
  93.         "bic r1, r1, #0x1f      \n"
  94.         "orr r1, r1, r0         \n"
  95.         "mrs r0, cpsr           \n"
  96.         "msr cpsr_c, r1         \n"
  97.  
  98.         "mov r3, r13            \n"
  99.         "stmfd r13!, {r2}       \n"
  100.         "mov r2, lr         \n"
  101.         "stmfd r13!, {r4-r12}       \n"
  102.         "mov r1, r13            \n"
  103.         /* the following two lines are for debugging */
  104.         "mov sp, #0         \n"
  105.         "mov lr, #0         \n"
  106.         "msr cpsr_c, r0         \n"
  107.  
  108.         "ldmfd r13!, {r4, r5, r6, r7}   \n"
  109.         "stmfd r1!, {r4, r5, r6}    \n"
  110.         "stmfd r1!, {r7}        \n"
  111.         "stmfd r1!, {r2}        \n"
  112.         "stmfd r1!, {r3}        \n"
  113.         "mrs r0, spsr           \n"
  114.         "stmfd r1!, {r0}        \n"
  115.         "mov r13, r1            \n"
  116.     "2:\n"
  117.     );
  118. }
  119.  
  120. /** Returns from exception mode.
  121.  *
  122.  * Previously saved state of registers (including control register)
  123.  * is restored from the stack.
  124.  */
  125. inline static void load_regs()
  126. {
  127.     asm volatile(
  128.         "ldmfd r13!, {r0}       \n"
  129.         "msr spsr, r0           \n"
  130.         "and r0, r0, #0x1f      \n"
  131.         "cmp r0, #0x10          \n"
  132.         "bne 1f             \n"
  133.  
  134.         /* return to user mode */
  135.         "ldmfd r13!, {r13, lr}^     \n"
  136.         "b 2f               \n"
  137.  
  138.         /* return to non-user mode */
  139.     "1:\n"
  140.         "ldmfd r13!, {r1, r2}       \n"
  141.         "mrs r3, cpsr           \n"
  142.         "bic r3, r3, #0x1f      \n"
  143.         "orr r3, r3, r0         \n"
  144.         "mrs r0, cpsr           \n"
  145.         "msr cpsr_c, r3         \n"
  146.  
  147.         "mov r13, r1            \n"
  148.         "mov lr, r2         \n"
  149.         "msr cpsr_c, r0         \n"
  150.  
  151.         /* actual return */
  152.     "2:\n"
  153.         "ldmfd r13, {r0-r12, pc}^\n"
  154.     );
  155. }
  156.  
  157.  
  158. /** Switch CPU to mode in which interrupts are serviced (currently it
  159.  * is Undefined mode).
  160.  *
  161.  * The default mode for interrupt servicing (Interrupt Mode)
  162.  * can not be used because of nested interrupts (which can occur
  163.  * because interrupts are enabled in higher levels of interrupt handler).
  164.  */
  165. inline static void switch_to_irq_servicing_mode()
  166. {
  167.     /* switch to Undefined mode */
  168.     asm volatile(
  169.         /* save regs used during switching */
  170.         "stmfd sp!, {r0-r3}     \n"
  171.  
  172.         /* save stack pointer and link register to r1, r2 */
  173.         "mov r1, sp         \n"
  174.         "mov r2, lr         \n"
  175.  
  176.         /* mode switch */
  177.         "mrs r0, cpsr           \n"
  178.         "bic r0, r0, #0x1f      \n"
  179.         "orr r0, r0, #0x1b      \n"
  180.         "msr cpsr_c, r0         \n"
  181.  
  182.         /* restore saved sp and lr */
  183.         "mov sp, r1         \n"
  184.         "mov lr, r2         \n"
  185.  
  186.         /* restore original regs */
  187.         "ldmfd sp!, {r0-r3}     \n"
  188.     );
  189. }
  190.  
  191. /** Calls exception dispatch routine. */
  192. #define CALL_EXC_DISPATCH(exception)        \
  193.     asm("mov r0, %0" : : "i" (exception));  \
  194.     asm("mov r1, r13");         \
  195.     asm("bl exc_dispatch");    
  196.  
  197. /** General exception handler.
  198.  *
  199.  *  Stores registers, dispatches the exception,
  200.  *  and finally restores registers and returns from exception processing.
  201.  *
  202.  *  @param exception Exception number.
  203.  */
  204. #define PROCESS_EXCEPTION(exception)        \
  205.     setup_stack_and_save_regs();        \
  206.     CALL_EXC_DISPATCH(exception)        \
  207.     load_regs();
  208.  
  209. /** Updates specified exception vector to jump to given handler.
  210.  *
  211.  *  Addresses of handlers are stored in memory following exception vectors.
  212.  */
  213. static void install_handler (unsigned handler_addr, unsigned* vector)
  214. {
  215.     /* relative address (related to exc. vector) of the word
  216.      * where handler's address is stored
  217.     */
  218.     volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -
  219.         PREFETCH_OFFSET;
  220.    
  221.     /* make it LDR instruction and store at exception vector */
  222.     *vector = handler_address_ptr | LDR_OPCODE;
  223.    
  224.     /* store handler's address */
  225.     *(vector + EXC_VECTORS) = handler_addr;
  226.  
  227. }
  228.  
  229. /** Low-level Reset Exception handler. */
  230. static void reset_exception_entry()
  231. {
  232.     PROCESS_EXCEPTION(EXC_RESET);
  233. }
  234.  
  235. /** Low-level Software Interrupt Exception handler. */
  236. static void swi_exception_entry()
  237. {
  238.     PROCESS_EXCEPTION(EXC_SWI);
  239. }
  240.  
  241. /** Low-level Undefined Instruction Exception handler. */
  242. static void undef_instr_exception_entry()
  243. {
  244.     PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
  245. }
  246.  
  247. /** Low-level Fast Interrupt Exception handler. */
  248. static void fiq_exception_entry()
  249. {
  250.     PROCESS_EXCEPTION(EXC_FIQ);
  251. }
  252.  
  253. /** Low-level Prefetch Abort Exception handler. */
  254. static void prefetch_abort_exception_entry()
  255. {
  256.     asm("sub lr, lr, #4");
  257.     PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
  258. }
  259.  
  260. /** Low-level Data Abort Exception handler. */
  261. static void data_abort_exception_entry()
  262. {
  263.     asm("sub lr, lr, #8");
  264.     PROCESS_EXCEPTION(EXC_DATA_ABORT);
  265. }
  266.  
  267. /** Low-level Interrupt Exception handler.
  268.  *
  269.  * CPU is switched to Undefined mode before further interrupt processing
  270.  * because of possible occurence of nested interrupt exception, which
  271.  * would overwrite (and thus spoil) stack pointer.
  272.  */
  273. static void irq_exception_entry()
  274. {
  275.     asm("sub lr, lr, #4");
  276.     setup_stack_and_save_regs();
  277.    
  278.     switch_to_irq_servicing_mode();
  279.    
  280.     CALL_EXC_DISPATCH(EXC_IRQ)
  281.  
  282.     load_regs();
  283. }
  284.  
  285. /** Software Interrupt handler.
  286.  *
  287.  * Dispatches the syscall.
  288.  */
  289. static void swi_exception(int exc_no, istate_t *istate)
  290. {
  291.     istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2,
  292.         istate->r3, istate->r4, istate->r5, istate->r6);
  293. }
  294.  
  295. /** Interrupt Exception handler.
  296.  *
  297.  * Determines the sources of interrupt and calls their handlers.
  298.  */
  299. static void irq_exception(int exc_no, istate_t *istate)
  300. {
  301.     machine_irq_exception(exc_no, istate);
  302. }
  303.  
  304. /** Fills exception vectors with appropriate exception handlers. */
  305. void install_exception_handlers(void)
  306. {
  307.     install_handler((unsigned) reset_exception_entry,
  308.         (unsigned *) EXC_RESET_VEC);
  309.    
  310.     install_handler((unsigned) undef_instr_exception_entry,
  311.         (unsigned *) EXC_UNDEF_INSTR_VEC);
  312.    
  313.     install_handler((unsigned) swi_exception_entry,
  314.         (unsigned *) EXC_SWI_VEC);
  315.    
  316.     install_handler((unsigned) prefetch_abort_exception_entry,
  317.         (unsigned *) EXC_PREFETCH_ABORT_VEC);
  318.    
  319.     install_handler((unsigned) data_abort_exception_entry,
  320.         (unsigned *) EXC_DATA_ABORT_VEC);
  321.    
  322.     install_handler((unsigned) irq_exception_entry,
  323.         (unsigned *) EXC_IRQ_VEC);
  324.    
  325.     install_handler((unsigned)fiq_exception_entry,
  326.         (unsigned *) EXC_FIQ_VEC);
  327. }
  328.  
  329. #ifdef HIGH_EXCEPTION_VECTORS
  330. /** Activates use of high exception vectors addresses. */
  331. static void high_vectors(void)
  332. {
  333.     uint32_t control_reg;
  334.    
  335.     asm volatile("mrc p15, 0, %0, c1, c1" : "=r" (control_reg));
  336.    
  337.     /* switch on the high vectors bit */
  338.     control_reg |= CP15_R1_HIGH_VECTORS_BIT;
  339.    
  340.     asm volatile("mcr p15, 0, %0, c1, c1" : : "r" (control_reg));
  341. }
  342. #endif
  343.  
  344. /** Initializes exception handling.
  345.  *
  346.  * Installs low-level exception handlers and then registers
  347.  * exceptions and their handlers to kernel exception dispatcher.
  348.  */
  349. void exception_init(void)
  350. {
  351. #ifdef HIGH_EXCEPTION_VECTORS
  352.     high_vectors();
  353. #endif
  354.     install_exception_handlers();
  355.    
  356.     exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
  357.     exc_register(EXC_PREFETCH_ABORT, "prefetch abort",
  358.         (iroutine) prefetch_abort);
  359.     exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
  360.     exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
  361. }
  362.  
  363. /** Prints #istate_t structure content.
  364.  *
  365.  * @param istate Structure to be printed.
  366.  */
  367. void print_istate(istate_t *istate)
  368. {
  369.     dprintf("istate dump:\n");
  370.  
  371.     dprintf(" r0: %x    r1: %x    r2: %x    r3: %x\n",
  372.         istate->r0, istate->r1, istate->r2, istate->r3);
  373.     dprintf(" r4: %x    r5: %x    r6: %x    r7: %x\n",
  374.         istate->r4, istate->r5, istate->r6, istate->r7);
  375.     dprintf(" r8: %x    r8: %x   r10: %x   r11: %x\n",
  376.         istate->r8, istate->r9, istate->r10, istate->r11);
  377.     dprintf(" r12: %x    sp: %x    lr: %x  spsr: %x\n",
  378.         istate->r12, istate->sp, istate->lr, istate->spsr);
  379.  
  380.     dprintf(" pc: %x\n", istate->pc);
  381. }
  382.  
  383. /** @}
  384.  */
  385.